Lpc2000

> Have you considered implementing your interface via
> PLD (CPLD/FPGA) based
> state machine?

I use a CPLD now, it generates the external interrupt
from an address range asserted by another processor. 
That frees my ARM up from making a bunch of
comparisons and memory fetches.  I am not able to move
all the processing to a CPLD because of the diverse
responses the project requires.  My ARM uses an 8K
jump table to react to its input.  I know, thats a
huge table and many of the locations wont be used, but
I need a deterministic response over all of them. 
Even though I only use a small percentage of the
location at any one time, I dynamically reconfigure
them during execution.  So it many be possible to have
all of them used at least once.

Cost is of the highest priority, so a powerful enough
FPGAs may be out of the question.  Beyond that, I dont
think I am capable of creating a useful core.

I am looking into a couple ARM9s.  Is there such a
thing as an ARM9 with local flash/SRAM?  I think I
read a press release from Philips a while back for
chip like this, something like an LPC3000 maybe.  I
havent been able to find anything concrete, so figure
it wont be available anytime soon anyway.

Thanks for the suggestion.

Vern



		
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