Lpc2000

itsjustimpossible wrote:
> Hi
> I need to interface an FPGA to the external bus of the LPC2294 so 
> that I can directly read and write to the BlockRam internal to the 
> FPGA (Arranged as a dual-port RAM).
> 
> I just wondered if someone has already achieved this or knows of 
> some example VHDL they can point me at. We are very new to this, 
> just attended a VHDL course, and am wondering about the correct way 
> to go about it.
> 
> The XCLK seems to be the key to this, but I am currently trying to 
> sort out how to handle the control lines and the tri-state buffers.
> 
> The statement in the data sheet that is causing me a problem is 
> the "CS and OE lines may become low one XCLK earlier than is shown". 
> I assume then that I cannot use these lines directly as the address 
> bus may not be stable at that point.
> 
> I know this is probably blindingly obvious, but if anyone has some 
> pointers for a novice I would be very grateful.
> 
> If it makes any difference I am using an Altera Stratix.

Hey Simon,

I have planned to interface an FPGA to an LPC part, but haven't had
time (I just tinker with the parts). If you want some help with the
interface, take a shot at it and let me know. I have the Altera tools
setup here and Mentor's ModelSim etc. The first thing you should try
and do is build a bus-functional-model (BFM) of the LPC external bus.
Basically you use non-synthesisable VHDL constructs (like time delays)
to implement the bus signal timing for a read, and then for a write.
Then you write your Stratix interface and write a test bench
to use the BFM to write and read to your Stratix i/f. If that works,
then it'll (usually) work on the real hardware (sometimes you
need to iterate to get a valid BFM).

Cheers
Dave