Lpc2000

On 10 Jan 2006 at 12:33, itsjustimpossible wrote:

> Hi
> I need to interface an FPGA to the external bus of the LPC2294 so that
> I can directly read and write to the BlockRam internal to the FPGA
> (Arranged as a dual-port RAM).
> 
> I just wondered if someone has already achieved this or knows of some
> example VHDL they can point me at. We are very new to this, just
> attended a VHDL course, and am wondering about the correct way to go
> about it.
> 
> The XCLK seems to be the key to this, but I am currently trying to
> sort out how to handle the control lines and the tri-state buffers.
> 
> The statement in the data sheet that is causing me a problem is 
> the "CS and OE lines may become low one XCLK earlier than is shown". I
> assume then that I cannot use these lines directly as the address bus
> may not be stable at that point.
> 
> I know this is probably blindingly obvious, but if anyone has some
> pointers for a novice I would be very grateful.
> 
> If it makes any difference I am using an Altera Stratix.


The external bus is an async bus. When writing use the write strobes as the 
"clock" signal that clocks the data into the specific RAM location. 
Use the external CS signal to qualify the internal CS signal based on the address
bus. i.e. the output of the comparator block goes through a 2 to 1 mux using the 
external CS signal as the select signal.
 Do you want to be able to handle various bus-width accesses, mis-aligned 
access etc. ? The easiest is to allow only one size access (aligned),  whether it is 
8, 16 or 32 bit. If you want to be able to handle all possible bus transactions, 
then the complexity increases dramatically. Another problem if you are 
accessing dual port RAM is that the LPC2294 does not have a "wait" signal 
where you can stretch the access cycle if the other side is trying to access the 
same address at the same time. You will need to implement some sort of 
semaphore in the FPGA with which you can grant access to the dual port RAM 
to either the one bus or the other bus. If you have simultaneous access from both 
sides you WILL have problems. 

Regards
  Anton Erasmus



-- 
A J Erasmus


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