Lpc2000

Thank you for all the suggestions. I have put together an initial
schematic diagram using 74VHC14 schmitt trigger inverters and RC low
pass filters (as suggested here):

http://www.k9spud.com/jtag/

I'm not sure how to add additional signals like RTCK and nTRST. Won't
these kind of changes require software support on the PC to be useful?
My understanding was that the Macraigor software was not open source.
Where should these signals be connected to on the PC side?

Or are you just suggesting a jumper for the user to manually switch by
hand?

What is the nTRST signal useful for? I'm new to JTAG, just trying to
get my first ARM project started.

--- In lpc2000@yahoogroups.com, "Arie de Muynck" <mygroups@x...> wrote:
>
> From: "Bertrik Sikken" <bertrik@z...>
> > Perhaps we can improve upon the existing designs and create
> > the ultimate low-cost ARM JTAG cable, yet keeping it simple.
> > Some ideas:
> > * provide proper current limiting for all lines
> > * add readback of the RTCK signal (return clock)
> > * add readback of the targets' VCC (like the Olimex clone does)
> 
> Also:
> 
> * use proper level shifting buffers or separate buffers for the LPT port
>   side(5V logic) and the target side (target voltage).
> * use low-pass filters (RC) + schmidttrigger receivers on the LPT
port side.
> * series termination resistor on each driven line, to LPT and to target.
> * a (jumper selectable) nTRST drive, separate from the nRESET drive.
> * optional: a 1mA LED indicator on the target side VCC.
> 
> The problems occur not just with building the thing - it's the wiggler
> design itself that is a bit flakey, especially the lack of a noise
filter
> and schmidttrigger receiver on the CLK input at the LPT side. A
100...400
> nsec RC filter should do it while still allowing up to 1 MHz
clocking (above
> LPT port speed levels). If this is not present, long LPT cables or
improper
> grounding will cause glitches that upset the JTAG state machine.
> 
> I fail to see the actual use of the RTCK signal - is this to be
tested by SW
> on the LPT status bits? Which CPU is so slow that this would make a
> difference?