Lpc2000

--- In lpc2000@yahoogroups.com, David Hawkins <dwh@o...> wrote:
<snip>
> You might just have to setup the LPC wait-states.

I did have to set WST1=1 and WST2=1 in the LPC, this gives one more 
clock cycle per access and seemed to help a lot.

> 
> The downside of the LPC implementation of their external bus
> interface is that you can't force the processor to wait for a
> variable number of cycles (via a WAIT# input pin).
<snip>

Luckily the wait state part is not a problem in this case (well not 
so far anyway).

> 
> Cheers
> Dave
>

I now have it working and have tried to incorporate as many 
suggestions as possible. Only problem is it looks a bit too 
straightforward to be true (safe).

I am using an XCLK of 60MHz multiplied by 4 in the FPGA and fed to 
the blockRam.
An option in the blockRam allows all inputs and outputs to be 
registered so I have connected its address and data input busses 
directly to the uP busses. After this it seems the only thing left 
to do is generate a 'WriteNow' and 'ReadNow' signal to be fed to the 
BlockRam and to tri-state the data output bus.

This is all there is...

	P_uP_INTERFACE: process (tl_ReadNow, tl_RAM_DATA_OUT)
	begin
	
		if (tl_ReadNow = '1') then
			tl_DataIn <= tl_RAM_DATA_OUT;	
		else
			tl_DataIn <= (others => 'Z');
		end if;
	
	end process P_uP_INTERFACE;

---------------------------------------------------
  
  tl_WriteNow <= (not tl_CSIn) and (not tl_BLSOIn);

  tl_ReadNow  <= (not tl_CSIn) and (not tl_OEIn);


Simulates OK and seems to work in practice. Just seems a bit un-
complicated.

Thanks for the help so far, if you have any comments they would be 
greatly appreciated.

Many thanks

Simon