Lpc2000

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Arie de Muynck wrote:
> From: "Bertrik Sikken" <bertrik@...>
>> Perhaps we can improve upon the existing designs and create
>> the ultimate low-cost ARM JTAG cable, yet keeping it simple.
>> Some ideas:
>> * provide proper current limiting for all lines
>> * add readback of the RTCK signal (return clock)
>> * add readback of the targets' VCC (like the Olimex clone does)
> 
> Also:
> 
> * use proper level shifting buffers or separate buffers for the LPT port
>   side(5V logic) and the target side (target voltage).
> * use low-pass filters (RC) + schmidttrigger receivers on the LPT port side.
> * series termination resistor on each driven line, to LPT and to target.
> * a (jumper selectable) nTRST drive, separate from the nRESET drive.
> * optional: a 1mA LED indicator on the target side VCC.
> 
> The problems occur not just with building the thing - it's the wiggler
> design itself that is a bit flakey, especially the lack of a noise filter
> and schmidttrigger receiver on the CLK input at the LPT side. A 100...400
> nsec RC filter should do it while still allowing up to 1 MHz clocking (above
> LPT port speed levels). If this is not present, long LPT cables or improper
> grounding will cause glitches that upset the JTAG state machine.
> 
> I fail to see the actual use of the RTCK signal - is this to be tested by SW
> on the LPT status bits? Which CPU is so slow that this would make a
> difference?

Well, if there are spare pins on the parallel port, unconnected pins
on the JTAG connector and unused buffers in the line driver, then
why _not_ just connect them?

We could use the RTCK pin to check if JTAG is echoing TCK properly
or not. Or it could be used to check if RTCK is indeed pulled-down
during reset (required for the LPC2148 for example).
I don't know if the RTCK can in practice be used to actually check
synchronisation with TCK, or how slow a CPU needs to be for that.

Ofcourse, if the goal is just to build an exact wiggler clone,
there's no need for it.

Regards,
Bertrik

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