Lpc2000

That's what everyone else seems to do... The original wiggler clone
schematic had it that way, the Olimex development boards seem to have
both pins 1&2 tied to target VDD, etc.

--- In lpc2000@yahoogroups.com, "Soentgerath, Guido"
<Guido.Soentgerath@s...> wrote:

> just one question:
> why do you connect pin 2 of the jtag connector with VDD ?
> 
> From: lpc2000@yahoogroups.com [mailto:lpc2000@yahoogroups.com] On Behalf
> Of Ed Schlunder
> Sent: Freitag, 20. Januar 2006 09:28
> To: lpc2000@yahoogroups.com
> Subject: [lpc2000] Re: Building DIY wiggler w/74VHC14
> 
> 
> I've been doing some more research on adding the nTRST signal to the
> DIY wiggler. 
> 
> http://www.macraigor.com/downloads/pinouts.pdf
> http://sourceforge.net/tracker/index.php?func=detail&aid=799377&group_id
> =52603&atid=469852
> 
> According to the above links, it looks like the genuine wiggler
> actually already has support for driving the nTRST JTAG signal from
> the parallel port's DATA4 pin. 
> 
> The existing DIY wiggler clone schematics have no connection of DATA4
> to nTRST like the real wiggler appearantly has. Could this be why DIY
> wiggler clones flake out on people? 
> 
> Here's the relevant section of ARM Application Note 31
> (http://www.arm.com/pdfs/DAI0031C_using_eice.pdf):
> 
> "nRESET is used to reset the processor core and put it into a known
> state, while nTRST is used to reset the TAP controller and the
> EmbeddedICE macrocell, including the registers in the
> breakpoint/watchpoint units. Both these resets must be applied before
> the device will function correctly."
> 
> So, without any circuitry to drive nTRST, the TAP controller could end
> up in an unusable state where the host can not communicate with the
> JTAG port. Doing a nRESET, which is all the DIY wiggler has control
> over, would reset the processor core but never reset the TAP
> controller used for JTAG debugging.
> 
> I don't have a real wiggler, but given that the Macraigor pinouts PDF
> file shows the nTRST pin as being type "i" instead of type "oc" like
> the nRESET pin, I'm guessing that the nTRST signal should be connected
> to the DATA4 pin using a line driver instead of an inverting open
> collector transistor circuit as used for the nRESET signal. 
> 
> I've updated my schematic diagram to include the proposed change for
> TRST:
> 
> http://www.k9spud.com/jtag/
> 
> --- In lpc2000@yahoogroups.com, "derbaier" <dershu@s...> wrote:
> >
> > --- In lpc2000@yahoogroups.com, "Ed Schlunder" <zilym@y...> wrote:
> > >
> > > Thank you for all the suggestions. I have put together an initial
> > > schematic diagram using 74VHC14 schmitt trigger inverters and RC low
> > > pass filters (as suggested here):
> > > 
> > > http://www.k9spud.com/jtag/
> > > 
> > > I'm not sure how to add additional signals like RTCK and nTRST.
> Won't
> > > these kind of changes require software support on the PC to be
> useful?
> > > My understanding was that the Macraigor software was not open
> source.
> > > Where should these signals be connected to on the PC side?
> > > 
> > > Or are you just suggesting a jumper for the user to manually switch
> by
> > > hand?
> > > 
> > > What is the nTRST signal useful for? I'm new to JTAG, just trying to
> > > get my first ARM project started.
> > > 
> > 
> > Ed, your use of 'HC14 parts is exactly the same as ARM did in their
> > Application Note 31.  IMHO, I think that you will find the RC time
> > constant of your filters to be much too long!  With such large
> > resistors, the input capacitance of the of the Schmitt triggers will
> > probably be plenty of low pass filtering!  Also, if you want to save a
> > few parts, you can replace the transistor inverter and it's assocoated
> > base resistors with one of your left over 'HC14s with a series diode
> > on it's output to convert it to an equivalent of an open drain output.
> > 
> > A1. The signal connections on the PC side are fixed by the closed
> > source Macraigor software, so added enhancements to the hardeware will
> > not have Macraigor software support. In any case, the Wiggler clock is
> > probably much too slow for RTCK to be very useful unless the target
> > ARM is being clocked at a much slower than normal speed. RTCK has been
> > VERY useful for very high speed JTAG debuggers like TRACE32.
> > 
> > A2. The nTRST signal is the JTAG TAP controller reset. The other reset
> > signal is for the rest of the hardware. In other words, ARM intended
> > for them to be separately resetable, as they explain in section 12.3
> > of Application Note 31.