Lpc2000

Hi, Dmitry. I am no ARM7 expert, but perhaps what you're looking for 
is this:

xxx_IRS:
        msr cpsr_c, #MODE_FIQ|FIQ_BIT|IRQ_BIT   ; @ switch to FIQ 
with ints dsbld.
        ... ISR code ...
        msr cpsr_c, #MODE_IRQ|FIQ_BIT|IRQ_BIT   ; @ back to IRQ mode
        subs pc,lr,#4                           ; @ return from 
interrupt

(Notice the use of SUBS instead of SUB). The S flag to SUB tells the 
µP to restore the saved mode register, thus switching back to user 
mode.

Of course this will work only if you don't nest FIQs or IRQs.

Guille

--- In lpc2000@yahoogroups.com, Dmitry Diky <ddiky@a...> wrote:
>
> Fellows,
> 
> In my application it is convenient to switch between IRQ and FIQ in 
some 
> interrupt service routine.
> As I know FIQ mode used banked r8-r14 registers and no registers 
have to be 
> saved on stack (providing I want to have the things working :)
> 
> So, when an IRQ interrupt occurs, I immediately enter to FIQ, then 
process my 
> interrupt request and then exit..
> 
> xxx_IRS:
> 	msr cpsr_c, #MODE_FIQ|FIQ_BIT|IRQ_BIT	; @ switch to FIQ 
with ints dsbld.
> 	... ISR code ...
> 	msr cpsr_c, #MODE_IRQ|FIQ_BIT|IRQ_BIT	; @ back to IRQ mode
> 	sub pc,lr,#4						; @ 
return from interrupt
> 
> Everything seems to be working except I am not sure what happens to 
CPSR of 
> the user mode. As I understand, when nIRQ is asserted, CPSR being 
copied to 
> SPSR_irq and on IRQ exit SPSR_irq -> CPSR_usr. But what happens 
when I switch 
> to FIQ and back? Does the CPU core copy cpsr_irq to spsr_fiq and 
back 
> or... ??? In a few words: will be user's CPSR kept alive with such 
IRQ 
> servicing scheme?
> 
> Thanks,
> Dmitry.
>