Lpc2000

As you are entering and leaving the exception in the same mode, and
given you are allowed to change modes when you have the privilege, I
do not see anything wrong with your code.

I do someting similar to stash context informatinon in FIQ bank (so
that the code is RAM independent) and had no problems with exceptions,
although I have no FIQ/IRQ type of exceptions.

--- In lpc2000@yahoogroups.com, Dmitry Diky <ddiky@a...> wrote:
> Everything seems to be working except I am not sure what happens to
CPSR of 
> the user mode. As I understand, when nIRQ is asserted, CPSR being
copied to 
> SPSR_irq and on IRQ exit SPSR_irq -> CPSR_usr. But what happens when
I switch 
> to FIQ and back? Does the CPU core copy cpsr_irq to spsr_fiq and back 
> or... ??? In a few words: will be user's CPSR kept alive with such IRQ 
> servicing scheme?