Lpc2000

Tom,

I expect to put a tantalum cap of perhaps 1uf or so on the voltage
divider junction and sample very infrequently, perhaps once per
second. Perhaps it is "no worries" about what the analog input leakage
current  is  in such circumstances.  If it is 4ua then the offset on a
100k  source  Z  would be only about 40mv and reflected up the divider
for  a  15  volt  max reading would equal a measurement error of about
200mv  which  is NOT inclusive of resistor tolerance errors.  However,
if  the leakage were actually specified and I knew the polarity of the
analog  input  leakage  current (and it did not change direction under
any  circumstances)  I  would  be able to design for a typical setting
with knowledge of the worst case parameters.

Without  such  information,  It is a "shot in the dark" as to what the
unit-to-unit error spread in production will be.  I do not like to use
pots  or  select-at-test  resistors.  I would much rather have a fully
characterized part.

As to the option of a unity gain amp in front of the input.. Added
cost, plus the added power drain make that option unattractive unless
I cannot get it to work otherwise.

Sutton



--- In lpc2000@yahoogroups.com, Tom Walsh <tom@...> wrote:
>
> Sutton Mehaffey wrote:
> 
> >Does anyone (or Philips Techs) know the max input current leakage of
> >the ADC channel input pins? 
> >
> >The LPC2148 datasheet says that the input leakage current is max 4uA,
> >but I am thinking that this MAY apply just to the digital signal pins.
> >We are trying to use one of the ADC channels in conjunction with a
> >very accurate voltage divider for determining battery voltage for a
> >battery powered application.
> >
> >We need the actual SPECIFICATION max of the input leakage current
> >(and the polarity if it can be depended upon) so as to be able to
> >calculate a worst case error.
> >  
> >
> Just some observations from the peanut gallery, FWIW.  I, too, have 
> noticed, what appears to be, a definate avoidance of giving complete 
> spec's regarding pin loading / source / sink current for the LPC2000 
> processors.  I generally see DC specs which contain a lot more detail 
> than that of the LPC2000s.  IMHO, this is deliberate?
> 
> 
> If they are using an approximation technique for measuring the voltage, 
> you may not have a consistant load presented by the ADC input. 
Assuming 
> that they are using a fixed resistance ladder with FET switches gating 
> the samples within the ladder may not be the case.  Therefore, the act 
> of performing a conversion may present you with a varying load?
> 
> I mean, if you are *that* sensitive to changes in load, then why not 
> eliminate them (Philips) from the unknowns and use a unity gain
buffer?  
> Place a simple op amp buffer between your voltage divider and the input 
> to the ADC.  Something with a FET input.  Done.  BUT, you still have
the 
> Common Mode spec of the op amp to contend with...
> 
> Otherwise, you may have to lower the "source" resistance (increase the 
> current through the divider) such that it is 10..20 times the max load 
> presented by the ADC input?  Look at it this way, if the voltage
divider 
> is drawing 1ma and the input to the ADC is @ 0.004ma (source vs load 
> ratio of 250), how much shift in the voltage would you see if  the ADC 
> input varied by 4ua (connect / disconnect)?  Having a load 1/250th of 
> the source is pretty darn negligable!  Kirchoff's Law...
> 
> If you are *that* sensitive to the 4ua load, perhaps your units would 
> need to be individually calibrated to match the processor's ADC input 
> load, op amp common mode, etc..  With the degree of accuracy you 
> suggest, this is probably the case in any event.
> 
> Regards,
> 
> TomW
> 
> 
> -- 
> Tom Walsh - WN3L - Embedded Systems Consultant
> http://openhardware.net, http://cyberiansoftware.com
> "Windows? No thanks, I have work to do..."
> ----------------------------------------------------
>