Lpc2000

--- In lpc2000@yahoogroups.com, "raweaver06" <raweaver00@...> wrote:
>
> --- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@> 
> wrote:
> >
> > Quoting raweaver06 <raweaver00@>:
> > 
> > > I'm looking into using ARM so I'm a newbie.  I currently use a
> > > processor that is 16 bits 30MIPS capable.  So seeing that ARM 
is 
> 32
> > > bits and 60 MIPS capable has me wanting.  I've read that real 
> world is
> > > actually 52 MIPS (still above my baseline 30 MIPS).  But then 
> I've seen
> > > where you have to run 1/4 speed out of FLASH.  So is the 52 
MIPS 
> number
> > > just running out of RAM?  I'll need most of my RAM for 
> application so I
> > > want the program to stay in FLASH.  Does running out of FLASH 
> mean 52/4
> > > for only 13 MIPS thruput.  I might as well stay with my current
> > > processor if so.  I might as well stop reading all of this ARM
> > > documentation if this is true.
> > 
> > A couple of things to point out.
> > 
> > Throughput and MIPS are quite different things. A 32 bit ARM at 
60 
> MIPs will
> > handle 32 bit arithmetic quite a bit faster than a 16 bit 
processor 
> at 
> > 30 MIPs.
> > Throughput (moving data to/from peripherals and I/O) depends 
highly 
> on the
> > implementation of the peripherals and items like DMA and Psuedo 
> DMA.  In
> > particular I/O bit twiddling is not an ARMs strong suit.
> > 
> > On the LPC running ARM code out of flash with the flash 
> acceleration options
> > turned on you get pretty close to full speed.  On other 
> implementations code
> > running out of flash will be slower simply because the flash is 
> slower 
> > or has a
> > 16 bit interface.  Running out of RAM also runs at full speed.
> > 
> > The 52 MIPs number is I think for running thumb code which is 
> prefered by some
> > for being more compact.  On implementations with 16 bit wide 
flash 
> interfaces
> > it will also speed up execution since only one memory acces needs 
> to be done
> > for each instruction fetch (not true for LPCs though).
> > 
> > That's either helped or I've confused you even more. :)
> > 
> > Robert
> >
> 
> My app's are typically very heavily math oriented (I will even use 
> software floating point more often with a strong CPU to speed up 
> development time) so a 32 bit architecture I feel will be of great 
> benefit here.  I don't do much I/O bit twiddling, mostly CAN I/0 
> communication which can now be done in two register reads instead 
of 
> my current 4.   So, now that I've been re-assured that LPC doesn't 
> carry much of a penalty in FLASH, I'll keep up my heavy reading in 
> ARM architucture and learning.  Thanks for the info.
>

It's a total different story when you need to use external flash:
 
Only 9.6 MIPS @60Mhz if you use 16 bit flash devices with an access 
time of 90nS and 25nS burstmode access time.
Only 6.7 MIPS @60Mhz if you use 16 bit flash devices with an access 
time of 90nS without burstmode access.
 
Patrick