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ARM Thruput expectations

ARM Thruput expectations

2006-03-15 by raweaver06

I'm looking into using ARM so I'm a newbie.  I currently use a 
processor that is 16 bits 30MIPS capable.  So seeing that ARM is 32 
bits and 60 MIPS capable has me wanting.  I've read that real world is 
actually 52 MIPS (still above my baseline 30 MIPS).  But then I've seen 
where you have to run 1/4 speed out of FLASH.  So is the 52 MIPS number 
just running out of RAM?  I'll need most of my RAM for application so I 
want the program to stay in FLASH.  Does running out of FLASH mean 52/4 
for only 13 MIPS thruput.  I might as well stay with my current 
processor if so.  I might as well stop reading all of this ARM 
documentation if this is true.

Re: [lpc2000] ARM Thruput expectations

2006-03-15 by K B Shah-lascaux

Running from Flash is also fast...
Look at pipeline architecture.... 
LPC series  from Philips semi. has memory accelerator module (MAM)  that allows instruction and data fetch in advance ...

 k b 
Show quoted textHide quoted text
  ----- Original Message ----- 
  From: raweaver06 
  To: lpc2000@yahoogroups.com 
  Sent: Wednesday, March 15, 2006 11:36 AM
  Subject: [lpc2000] ARM Thruput expectations


  I'm looking into using ARM so I'm a newbie.  I currently use a 
  processor that is 16 bits 30MIPS capable.  So seeing that ARM is 32 
  bits and 60 MIPS capable has me wanting.  I've read that real world is 
  actually 52 MIPS (still above my baseline 30 MIPS).  But then I've seen 
  where you have to run 1/4 speed out of FLASH.  So is the 52 MIPS number 
  just running out of RAM?  I'll need most of my RAM for application so I 
  want the program to stay in FLASH.  Does running out of FLASH mean 52/4 
  for only 13 MIPS thruput.  I might as well stay with my current 
  processor if so.  I might as well stop reading all of this ARM 
  documentation if this is true.





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Re: [lpc2000] ARM Thruput expectations

2006-03-15 by Robert Adsett

Quoting raweaver06 <raweaver00@...>:

> I'm looking into using ARM so I'm a newbie.  I currently use a
> processor that is 16 bits 30MIPS capable.  So seeing that ARM is 32
> bits and 60 MIPS capable has me wanting.  I've read that real world is
> actually 52 MIPS (still above my baseline 30 MIPS).  But then I've seen
> where you have to run 1/4 speed out of FLASH.  So is the 52 MIPS number
> just running out of RAM?  I'll need most of my RAM for application so I
> want the program to stay in FLASH.  Does running out of FLASH mean 52/4
> for only 13 MIPS thruput.  I might as well stay with my current
> processor if so.  I might as well stop reading all of this ARM
> documentation if this is true.

A couple of things to point out.

Throughput and MIPS are quite different things. A 32 bit ARM at 60 MIPs will
handle 32 bit arithmetic quite a bit faster than a 16 bit processor at 
30 MIPs.
Throughput (moving data to/from peripherals and I/O) depends highly on the
implementation of the peripherals and items like DMA and Psuedo DMA.  In
particular I/O bit twiddling is not an ARMs strong suit.

On the LPC running ARM code out of flash with the flash acceleration options
turned on you get pretty close to full speed.  On other implementations code
running out of flash will be slower simply because the flash is slower 
or has a
16 bit interface.  Running out of RAM also runs at full speed.

The 52 MIPs number is I think for running thumb code which is prefered by some
for being more compact.  On implementations with 16 bit wide flash interfaces
it will also speed up execution since only one memory acces needs to be done
for each instruction fetch (not true for LPCs though).

That's either helped or I've confused you even more. :)

Robert

Re: [lpc2000] ARM Thruput expectations

2006-03-15 by Leon Heller

----- Original Message ----- 
Show quoted textHide quoted text
From: "K B Shah-lascaux" <kbshah@...>
To: <lpc2000@yahoogroups.com>
Sent: Wednesday, March 15, 2006 5:02 PM
Subject: Re: [lpc2000] ARM Thruput expectations


> Running from Flash is also fast...
> Look at pipeline architecture....
> LPC series  from Philips semi. has memory accelerator module (MAM)  that 
> allows instruction and data fetch in advance ...
>
> k b
>  ----- Original Message ----- 
>  From: raweaver06
>  To: lpc2000@yahoogroups.com
>  Sent: Wednesday, March 15, 2006 11:36 AM
>  Subject: [lpc2000] ARM Thruput expectations
>
>
>  I'm looking into using ARM so I'm a newbie.  I currently use a
>  processor that is 16 bits 30MIPS capable.  So seeing that ARM is 32
>  bits and 60 MIPS capable has me wanting.  I've read that real world is
>  actually 52 MIPS (still above my baseline 30 MIPS).  But then I've seen
>  where you have to run 1/4 speed out of FLASH.  So is the 52 MIPS number
>  just running out of RAM?  I'll need most of my RAM for application so I
>  want the program to stay in FLASH.  Does running out of FLASH mean 52/4
>  for only 13 MIPS thruput.  I might as well stay with my current
>  processor if so.  I might as well stop reading all of this ARM
>  documentation if this is true.

The Philips ARM chips can run at full speed from flash, it has a128 bit 
interface which speeds it up. They can't toggle outputs very fast, the newer 
chips have faster I/O but it's still nothing like the instruction rate.

Leon

Re: ARM Thruput expectations

2006-03-15 by raweaver06

--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@...> 
wrote:
>
> Quoting raweaver06 <raweaver00@...>:
> 
> > I'm looking into using ARM so I'm a newbie.  I currently use a
> > processor that is 16 bits 30MIPS capable.  So seeing that ARM is 
32
> > bits and 60 MIPS capable has me wanting.  I've read that real 
world is
> > actually 52 MIPS (still above my baseline 30 MIPS).  But then 
I've seen
> > where you have to run 1/4 speed out of FLASH.  So is the 52 MIPS 
number
> > just running out of RAM?  I'll need most of my RAM for 
application so I
> > want the program to stay in FLASH.  Does running out of FLASH 
mean 52/4
> > for only 13 MIPS thruput.  I might as well stay with my current
> > processor if so.  I might as well stop reading all of this ARM
> > documentation if this is true.
> 
> A couple of things to point out.
> 
> Throughput and MIPS are quite different things. A 32 bit ARM at 60 
MIPs will
> handle 32 bit arithmetic quite a bit faster than a 16 bit processor 
at 
> 30 MIPs.
> Throughput (moving data to/from peripherals and I/O) depends highly 
on the
> implementation of the peripherals and items like DMA and Psuedo 
DMA.  In
> particular I/O bit twiddling is not an ARMs strong suit.
> 
> On the LPC running ARM code out of flash with the flash 
acceleration options
> turned on you get pretty close to full speed.  On other 
implementations code
> running out of flash will be slower simply because the flash is 
slower 
> or has a
> 16 bit interface.  Running out of RAM also runs at full speed.
> 
> The 52 MIPs number is I think for running thumb code which is 
prefered by some
> for being more compact.  On implementations with 16 bit wide flash 
interfaces
> it will also speed up execution since only one memory acces needs 
to be done
> for each instruction fetch (not true for LPCs though).
> 
> That's either helped or I've confused you even more. :)
> 
> Robert
>

My app's are typically very heavily math oriented (I will even use 
software floating point more often with a strong CPU to speed up 
development time) so a 32 bit architecture I feel will be of great 
benefit here.  I don't do much I/O bit twiddling, mostly CAN I/0 
communication which can now be done in two register reads instead of 
my current 4.   So, now that I've been re-assured that LPC doesn't 
carry much of a penalty in FLASH, I'll keep up my heavy reading in 
ARM architucture and learning.  Thanks for the info.

Re: ARM Thruput expectations

2006-03-15 by smoutpatrick

--- In lpc2000@yahoogroups.com, "raweaver06" <raweaver00@...> wrote:
>
> --- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@> 
> wrote:
> >
> > Quoting raweaver06 <raweaver00@>:
> > 
> > > I'm looking into using ARM so I'm a newbie.  I currently use a
> > > processor that is 16 bits 30MIPS capable.  So seeing that ARM 
is 
> 32
> > > bits and 60 MIPS capable has me wanting.  I've read that real 
> world is
> > > actually 52 MIPS (still above my baseline 30 MIPS).  But then 
> I've seen
> > > where you have to run 1/4 speed out of FLASH.  So is the 52 
MIPS 
> number
> > > just running out of RAM?  I'll need most of my RAM for 
> application so I
> > > want the program to stay in FLASH.  Does running out of FLASH 
> mean 52/4
> > > for only 13 MIPS thruput.  I might as well stay with my current
> > > processor if so.  I might as well stop reading all of this ARM
> > > documentation if this is true.
> > 
> > A couple of things to point out.
> > 
> > Throughput and MIPS are quite different things. A 32 bit ARM at 
60 
> MIPs will
> > handle 32 bit arithmetic quite a bit faster than a 16 bit 
processor 
> at 
> > 30 MIPs.
> > Throughput (moving data to/from peripherals and I/O) depends 
highly 
> on the
> > implementation of the peripherals and items like DMA and Psuedo 
> DMA.  In
> > particular I/O bit twiddling is not an ARMs strong suit.
> > 
> > On the LPC running ARM code out of flash with the flash 
> acceleration options
> > turned on you get pretty close to full speed.  On other 
> implementations code
> > running out of flash will be slower simply because the flash is 
> slower 
> > or has a
> > 16 bit interface.  Running out of RAM also runs at full speed.
> > 
> > The 52 MIPs number is I think for running thumb code which is 
> prefered by some
> > for being more compact.  On implementations with 16 bit wide 
flash 
> interfaces
> > it will also speed up execution since only one memory acces needs 
> to be done
> > for each instruction fetch (not true for LPCs though).
> > 
> > That's either helped or I've confused you even more. :)
> > 
> > Robert
> >
> 
> My app's are typically very heavily math oriented (I will even use 
> software floating point more often with a strong CPU to speed up 
> development time) so a 32 bit architecture I feel will be of great 
> benefit here.  I don't do much I/O bit twiddling, mostly CAN I/0 
> communication which can now be done in two register reads instead 
of 
> my current 4.   So, now that I've been re-assured that LPC doesn't 
> carry much of a penalty in FLASH, I'll keep up my heavy reading in 
> ARM architucture and learning.  Thanks for the info.
>

It's a total different story when you need to use external flash:
 
Only 9.6 MIPS @60Mhz if you use 16 bit flash devices with an access 
time of 90nS and 25nS burstmode access time.
Only 6.7 MIPS @60Mhz if you use 16 bit flash devices with an access 
time of 90nS without burstmode access.
 
Patrick

Re: ARM Thruput expectations

2006-03-15 by brendanmurphy37

--- In lpc2000@yahoogroups.com, "raweaver06" <raweaver00@...> wrote:
> My app's are typically very heavily math oriented (I will even use 
> software floating point more often with a strong CPU to speed up 
> development time) so a 32 bit architecture I feel will be of great 
> benefit here.  I don't do much I/O bit twiddling, mostly CAN I/0 
> communication which can now be done in two register reads instead of 
> my current 4.   So, now that I've been re-assured that LPC doesn't 
> carry much of a penalty in FLASH, I'll keep up my heavy reading in 
> ARM architucture and learning.  Thanks for the info.
>

Given what you say (heavy math, light bit-twiddling I/O), you should 
see a good improvement. Your figure of 52 MIPS for a 60 MHz clock is 
about right for the LPC2000 series (I believe some of the newer 
varients can be clocked even faster). The exact MIPS figure depends on 
the instruction mix: although it's called a RISC, in fact many ARM 
instructions take more than one cycle to complete. 

We did fairly extensive benchmarking of various 32-bit micros: the 
LPC2000 parts are pretty good. Note that you don't get 100% of the 
memory bandwidth with the MAM running from flash, but it's not far off 
it (again, exact figures hard to say, due to differences in the number 
of branches). Some other ARM parts are **very** slow running from 
flash.

Three other recommendations:

1. Given it's a 32-bit part, you might want to look at fixed-point 
math. A bit trickier to handle, but much faster on anything without 
floating-point hardware.

2. You might want to do some benchmarking on a simulator: again, from 
experience, published benchmarks mean little: you really need to look 
at what your application is doing. If you code up and measure the 
innermost loops you can get a fair idea of total MIPS.

3. Like all RISCS, compilers make a **huge** difference on ARM: with 
optimisation off, it'll run like a dog, with full optimisation, you'd 
be hard placed to hand-code in assembler more efficient code (I'm not 
saying you can't, but you probably don't have to bother). The downside 
is that debugging highly optimised code with an ICE can be quite a 
challange. Because of this we stick to ANSI 'C' and debug all our math 
stuff on a PC first.

Hope this helps.

By the way, what is the application area you're working on?

Brendan

Re: ARM Thruput expectations

2006-03-15 by raweaver06

--- In lpc2000@yahoogroups.com, "brendanmurphy37" 
<brendan.murphy@...> wrote:
>
> --- In lpc2000@yahoogroups.com, "raweaver06" <raweaver00@> wrote:
> > My app's are typically very heavily math oriented (I will even 
use 
> > software floating point more often with a strong CPU to speed up 
> > development time) so a 32 bit architecture I feel will be of 
great 
> > benefit here.  I don't do much I/O bit twiddling, mostly CAN I/0 
> > communication which can now be done in two register reads instead 
of 
> > my current 4.   So, now that I've been re-assured that LPC 
doesn't 
> > carry much of a penalty in FLASH, I'll keep up my heavy reading 
in 
> > ARM architucture and learning.  Thanks for the info.
> >
> 
> Given what you say (heavy math, light bit-twiddling I/O), you 
should 
> see a good improvement. Your figure of 52 MIPS for a 60 MHz clock 
is 
> about right for the LPC2000 series (I believe some of the newer 
> varients can be clocked even faster). The exact MIPS figure depends 
on 
> the instruction mix: although it's called a RISC, in fact many ARM 
> instructions take more than one cycle to complete. 
> 
> We did fairly extensive benchmarking of various 32-bit micros: the 
> LPC2000 parts are pretty good. Note that you don't get 100% of the 
> memory bandwidth with the MAM running from flash, but it's not far 
off 
> it (again, exact figures hard to say, due to differences in the 
number 
> of branches). Some other ARM parts are **very** slow running from 
> flash.
> 
> Three other recommendations:
> 
> 1. Given it's a 32-bit part, you might want to look at fixed-point 
> math. A bit trickier to handle, but much faster on anything without 
> floating-point hardware.
> 
> 2. You might want to do some benchmarking on a simulator: again, 
from 
> experience, published benchmarks mean little: you really need to 
look 
> at what your application is doing. If you code up and measure the 
> innermost loops you can get a fair idea of total MIPS.
> 
> 3. Like all RISCS, compilers make a **huge** difference on ARM: 
with 
> optimisation off, it'll run like a dog, with full optimisation, 
you'd 
> be hard placed to hand-code in assembler more efficient code (I'm 
not 
> saying you can't, but you probably don't have to bother). The 
downside 
> is that debugging highly optimised code with an ICE can be quite a 
> challange. Because of this we stick to ANSI 'C' and debug all our 
math 
> stuff on a PC first.
> 
> Hope this helps.
> 
> By the way, what is the application area you're working on?
> 
> Brendan
>

Sensor fusion, usually radars and now vision is to be added in.

Re: ARM Thruput expectations

2006-03-15 by lpc2100_fan

--- In lpc2000@yahoogroups.com, "Leon Heller" <leon.heller@...> wrote:
>
> ----- Original Message ----- 
> From: "K B Shah-lascaux" <kbshah@...>
> To: <lpc2000@yahoogroups.com>
> Sent: Wednesday, March 15, 2006 5:02 PM
> Subject: Re: [lpc2000] ARM Thruput expectations
> 
> 
> > Running from Flash is also fast...
> > Look at pipeline architecture....
> > LPC series  from Philips semi. has memory accelerator module (MAM)
 that 
> > allows instruction and data fetch in advance ...
> >
> > k b
> >  ----- Original Message ----- 
> >  From: raweaver06
> >  To: lpc2000@yahoogroups.com
> >  Sent: Wednesday, March 15, 2006 11:36 AM
> >  Subject: [lpc2000] ARM Thruput expectations
> >
> >
> >  I'm looking into using ARM so I'm a newbie.  I currently use a
> >  processor that is 16 bits 30MIPS capable.  So seeing that ARM is 32
> >  bits and 60 MIPS capable has me wanting.  I've read that real
world is
> >  actually 52 MIPS (still above my baseline 30 MIPS).  But then
I've seen
> >  where you have to run 1/4 speed out of FLASH.  So is the 52 MIPS
number
> >  just running out of RAM?  I'll need most of my RAM for
application so I
> >  want the program to stay in FLASH.  Does running out of FLASH
mean 52/4
> >  for only 13 MIPS thruput.  I might as well stay with my current
> >  processor if so.  I might as well stop reading all of this ARM
> >  documentation if this is true.
> 
> The Philips ARM chips can run at full speed from flash, it has a128 bit 
> interface which speeds it up. They can't toggle outputs very fast,
the newer 
> chips have faster I/O but it's still nothing like the instruction rate.
> 
> Leon
>

Hi Leon,

the newer versions with fast I/O can not toggle as fast as the
instruction rate, true, but half as fast!  So you can get a pin
toggled every other clock cycle resulting in a possible outpur
frequency of e.g. 60/4 = 15.

I happen to know that many people compare this to the AVR ;-) You
would need a 30 MHz AVR to do this.

Bob

Re: ARM Thruput expectations

2006-03-21 by jrweekes52

--- In lpc2000@yahoogroups.com, "lpc2100_fan" <lpc2100_fan@...> wrote:
>
> --- In lpc2000@yahoogroups.com, "Leon Heller" <leon.heller@> wrote:
> >
> > ----- Original Message ----- 
> > From: "K B Shah-lascaux" <kbshah@>
> > To: <lpc2000@yahoogroups.com>
> > Sent: Wednesday, March 15, 2006 5:02 PM
> > Subject: Re: [lpc2000] ARM Thruput expectations
> > 
> > 
> > > Running from Flash is also fast...
> > > Look at pipeline architecture....
> > > LPC series  from Philips semi. has memory accelerator module 
(MAM)
>  that 
> > > allows instruction and data fetch in advance ...
> > >
> > > k b
> > >  ----- Original Message ----- 
> > >  From: raweaver06
> > >  To: lpc2000@yahoogroups.com
> > >  Sent: Wednesday, March 15, 2006 11:36 AM
> > >  Subject: [lpc2000] ARM Thruput expectations
> > >
> > >
> > >  I'm looking into using ARM so I'm a newbie.  I currently use a
> > >  processor that is 16 bits 30MIPS capable.  So seeing that ARM 
is 32
> > >  bits and 60 MIPS capable has me wanting.  I've read that real
> world is
> > >  actually 52 MIPS (still above my baseline 30 MIPS).  But then
> I've seen
> > >  where you have to run 1/4 speed out of FLASH.  So is the 52 
MIPS
> number
> > >  just running out of RAM?  I'll need most of my RAM for
> application so I
> > >  want the program to stay in FLASH.  Does running out of FLASH
> mean 52/4
> > >  for only 13 MIPS thruput.  I might as well stay with my current
> > >  processor if so.  I might as well stop reading all of this ARM
> > >  documentation if this is true.
> > 
> > The Philips ARM chips can run at full speed from flash, it has 
a128 bit 
> > interface which speeds it up. They can't toggle outputs very fast,
> the newer 
> > chips have faster I/O but it's still nothing like the instruction 
rate.
> > 
> > Leon
> >
> 
> Hi Leon,
> 
> the newer versions with fast I/O can not toggle as fast as the
> instruction rate, true, but half as fast!  So you can get a pin
> toggled every other clock cycle resulting in a possible outpur
> frequency of e.g. 60/4 = 15.
> 
> I happen to know that many people compare this to the AVR ;-) You
> would need a 30 MHz AVR to do this.
> 
> Bob
>
Newer AVRs can toggle a pin in 1 cycle ;-) Aren't comparisons 
wonderful.

Jim

Re: ARM Thruput expectations

2006-03-21 by lpc2100_fan

> > Hi Leon,
> > 
> > the newer versions with fast I/O can not toggle as fast as the
> > instruction rate, true, but half as fast!  So you can get a pin
> > toggled every other clock cycle resulting in a possible output
> > frequency of e.g. 60/4 = 15.
> > 
> > I happen to know that many people compare this to the AVR ;-) You
> > would need a 30 MHz AVR to do this.
> > 
> > Bob
> >
> Newer AVRs can toggle a pin in 1 cycle ;-) Aren't comparisons 
> wonderful.
> 
> Jim
>
Hello Jim,

exactly what I wrote. To get a frequency of 60/4 you need to toggle
TWICE in 4 clocks. If you tell me that a 16 MHz AVR can generate more
than 8 MHz output that would really be news to me because that would
be 2 instructions in one cycle, a superscalar AVR8. 

Please no offense, I think it was only a misunderstanding in wording. 
And still the ARM needs 2 cycles to toggle a pin while the AVR does it
in one, it's just a fact that the ARM can almost run four cycles
before the AVR is done with one. 

The only reason I am comparing this to the AVR because the older
devices which needed 8 cycles to toggle a pin were actually slower in
toggeling than a 16 MHz AVR and that has been a major complaint in
this forum back then. 

Bob

Re: ARM Thruput expectations

2006-03-22 by jrweekes52

--- In lpc2000@yahoogroups.com, "lpc2100_fan" <lpc2100_fan@...> wrote:
>
>  
> > > Hi Leon,
> > > 
> > > the newer versions with fast I/O can not toggle as fast as the
> > > instruction rate, true, but half as fast!  So you can get a pin
> > > toggled every other clock cycle resulting in a possible output
> > > frequency of e.g. 60/4 = 15.
> > > 
> > > I happen to know that many people compare this to the AVR ;-) 
You
> > > would need a 30 MHz AVR to do this.
> > > 
> > > Bob
> > >
> > Newer AVRs can toggle a pin in 1 cycle ;-) Aren't comparisons 
> > wonderful.
> > 
> > Jim
> >
> Hello Jim,
> 
> exactly what I wrote. To get a frequency of 60/4 you need to toggle
> TWICE in 4 clocks. If you tell me that a 16 MHz AVR can generate 
more
> than 8 MHz output that would really be news to me because that would
> be 2 instructions in one cycle, a superscalar AVR8. 
> 
> Please no offense, I think it was only a misunderstanding in 
wording. 
> And still the ARM needs 2 cycles to toggle a pin while the AVR does 
it
> in one, it's just a fact that the ARM can almost run four cycles
> before the AVR is done with one. 
> 
> The only reason I am comparing this to the AVR because the older
> devices which needed 8 cycles to toggle a pin were actually slower 
in
> toggeling than a 16 MHz AVR and that has been a major complaint in
> this forum back then. 
> 
> Bob
>
Hello Bob,

No offense taken, I simply, as you say, misunderstood what you meant. 
Anyway it's good to see that newer LPCs can produce some reasonable I/
O toggle rates, something that put me off them at first.

Jim

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