Lpc2000

Hello:

First of all, thanks for your fast response.

I had tried what you say, but with the same results. What I do is 
include this file in my project (I'm not usign GNU-GCC but IAR):

MODE_BITS	DEFINE	0x1F		; Bit mask for mode bits in 
CPSR
USR_MODE	DEFINE	0x10		; User mode
FIQ_MODE	DEFINE	0x11		; Fast Interrupt Request mode
IRQ_MODE	DEFINE	0x12		; Interrupt Request mode
SVC_MODE	DEFINE	0x13		; Supervisor mode
ABT_MODE	DEFINE	0x17		; Abort mode
UND_MODE	DEFINE	0x1B		; Undefined Instruction mode
SYS_MODE	DEFINE	0x1F		; System mode
	

;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;---------------------------------------------------------------

		MODULE	?RESET
		COMMON	INTVEC:CODE:NOROOT(2)
		PUBLIC  __program_start
		EXTERN	?cstartup
;		EXTERN	undef_handler, swi_handler, prefetch_handler
;		EXTERN	data_handler, fiq_handler
;		EXTERN	irq_handler
		CODE32	; Always ARM mode after reset	
		org	0x00
__program_start
		ldr	pc,=?cstartup  ; Absolute jump can reach 4 
GByte
;		ldr	b,?cstartup    ; Relative branch allows 
remap, limited to 32 MByte
		org	0x04
undef_handler	ldr	pc,=undef_handler
		org	0x08
swi_handler	ldr	pc,=swi_handler
		org	0x0c
prefetch_handler ldr	pc,=prefetch_handler
		org	0x10
data_handler	ldr	pc,=data_handler
		org	0x18
irq_handler	ldr	pc,=irq_handler
		org	0x1c
fiq_handler	ldr	pc,=fiq_handler

		; Constant table entries (for ldr pc) will be placed 
at 0x20
		org	0x20
		LTORG
;		ENDMOD	__program_start
                ENDMOD


;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
		MODULE	?CSTARTUP

		RSEG	IRQ_STACK:DATA(2)
		RSEG	SVC_STACK:DATA:NOROOT(2)
		RSEG	CSTACK:DATA(2)
		RSEG	ICODE:CODE:NOROOT(2)
		PUBLIC	?cstartup
		EXTERN	?main

; Execution starts here.
; After a reset, the mode is ARM, Supervisor, interrupts disabled.


		CODE32
?cstartup

; Add initialization nedded before setup of stackpointers here


; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
                mrs     r0,cpsr                             ; 
Original PSR value
                bic     r0,r0,#MODE_BITS                    ; Clear 
the mode bits
                orr     r0,r0,#IRQ_MODE                     ; Set IRQ 
mode bits
                msr     cpsr_c,r0                           ; Change 
the mode
                ldr     sp,=SFE(IRQ_STACK) & 0xFFFFFFF8     ; End of 
IRQ_STACK

                bic     r0,r0,#MODE_BITS                    ; Clear 
the mode bits
                orr     r0,r0,#SYS_MODE                     ; Set 
System mode bits
                msr     cpsr_c,r0                           ; Change 
the mode
                ldr     sp,=SFE(CSTACK) & 0xFFFFFFF8        ; End of 
CSTACK

#ifdef __ARMVFP__
; Enable the VFP coprocessor.
                mov     r0, #0x40000000                 ; Set EN bit 
in VFP
                fmxr    fpexc, r0                       ; FPEXC, 
clear others.

; Disable underflow exceptions by setting flush to zero mode.
; For full IEEE 754 underflow compliance this code should be removed
; and the appropriate exception handler installed.
                mov     r0, #0x01000000		        ; Set FZ bit 
in VFP
                fmxr    fpscr, r0                       ; FPSCR, 
clear others.
#endif

; Add more initialization here


; Continue to ?main for more IAR specific system startup

                ldr     r0,=?main
                bx      r0

                LTORG

                ENDMOD


                END


This is a file called TinyC_Start_LPC210X or something similar and 
that cames with IAR, and they use for they LPC2106 demo project.

Anyway, I could not work with my program, since it still runs the 
bootloader. In the dissasembly window, I could see that:

__program_start:
  00000000  00000000  ANDEQ        R0, R0, R0               ; RESET 
undef_handler ldr pc,=undef_handler
undef_handler:
  00000004  00000004  ANDEQ        R0, R0, R4               ; UND   
swi_handler ldr pc,=swi_handler
swi_handler:
  00000008  00000008  ANDEQ        R0, R0, R8               ; SWI   
prefetch_handler ldr pc,=prefetch_handler
prefetch_handler:
  0000000C  0000000C  ANDEQ        R0, R0, R12              ; P ABT 
data_handler ldr pc,=data_handler
data_handler:
  00000010  00000010  ANDEQ        R0, R0, R0, LSL R0       ; D ABT 
  00000014  00000014  ANDEQ        R0, R0, R4, LSL R0
irq_handler ldr pc,=irq_handler
irq_handler:
  00000018  00000018  ANDEQ        R0, R0, R8, LSL R0       ; IRQ   
fiq_handler ldr pc,=fiq_handler
fiq_handler:
  0000001C  0000001C  ANDEQ        R0, R0, R12, LSL R0      ; FIQ   
_?0:
  00000020  00000020  ANDEQ        R0, R0, R0, LSR #32
_?1:
  00000024  00000024  ANDEQ        R0, R0, R4, LSR #32
_?2:
  00000028  00000028  ANDEQ        R0, R0, R8, LSR #32
_?3:
  0000002C  0000002C  ANDEQ        R0, R0, R12, LSR #32
_?4:
  00000030  00000030  ANDEQ        R0, R0, R0, LSR R0
_?5:
  00000034  00000034  ANDEQ        R0, R0, R4, LSR R0
_?6:
  00000038  00000038  ANDEQ        R0, R0, R8, LSR R0
  0000003C  0000003C  ANDEQ        R0, R0, R12, LSR R0

so this looks like the checksum is not loaded.

Any suggestions?

Thanks again,

Guillem Planisi.