Lpc2000

Joerg

Again, thanks for your advice. I too am a bit surprised about the 8ns 
rise time. The XCLK signal is driving a FPGA global clock which has 
configurable voltage input thresholds - 3.3v CMOS, TTL, etc. I've 
tried selecting different standards but the result is the same. 

I don't think the scope is influencing things significantly as I've 
observed faster & better quality waveforms. However I'm keen to try 
the coax connector & divider trick you described. I'm not 100% clear 
of the configuration though. Could you talk me through the setup ?

Regards
Dave

wrote:
>
> Hello Dave,
> 
> > 
> > Using a very short ground probe I've got an improved waveform 2.5V 
pk-
> > pk but asymmetrical, where the fall time is approx 3ns and the 
rise 
> > time is about 8ns.  
> > 
> 
> Again, I don't know the LPC2214 but 3nsec is possibly all it can do.
> Usually the output devices in a CMOS chip are similar so I don't 
quite
> get why rise and fall times are different, at least not if you are
> driving a CMOS chip with it. Looking at table 10 in the datasheet it
> appears that the LPC's outputs are symmetrical in device geometry.
> 
> With symmetrical CMOS on both sides uneven rise and fall times
> typically happen when you run into a substrate diode, for example 
when
> the supply voltages are different.
> 
> 
> > Removing the load improves the risetime and I get ~3v pk-pk. My 
scope 
> > has a 200MHz b/w & I've looked at a 70MHz clock on another board & 
I'm 
> > seeing a nice clean squarewave so I'm happy that the scope isn't 
> > giving a false picture. It does seem that the XCLK pin is having a 
> > hard time driving the load. 
> > 
> 
> A brief look at chapter 9 of the datasheet states 10nsec for the
> ports, not sure if that holds for XCLK but should be less. I don't
> know your configuration but a look at the fosc section could 
indicate
> that you are really pushing it with those 59MHz. If you are running 
at
> 3.3V supply then 3Vpp isn't all that bad. Table 10 states that worst
> case a port is 400mV off the respective rail at 4mA source resp. 
sink.
> This indicates that the output devices should be 100ohms or less. 
Into
> a 10pF load that would be about a couple nsec to swing well past the
> opposite digital threshold (time constant of 1nsec). Considering 
that
> whatever drives it internally isn't infinitely fast you might be
> looking at 3nsec or more. This still does not explain your 8nsec 
rise
> time. Something must be in the circuit that wants to hold it down.
> 
> 
> > I've doubled checked the datasheet & the load input capacitance is 
> > 10pF max. The clock trace is on the top layer & is ~15mm long, 
12mil 
> > wide with no vias. There is a groundplane on the next layer.
> > 
> 
> 15mm is next to nothing, less than a pF depending on the prepreg
> between plane and layer. So there should not be any worries there.
> 
> 
> > Do you have any other suggestions ?
> > 
> 
> I'd try the coax and divider trick to eliminate the scope probe
> uncertainty. Changing the length of the ground made a difference as
> you had seen. At 50MHz there should not be a ground clip at all, the
> coax shield should tie into ground less than 5mm from where you want
> to measure. I use a Philips FET probe for that which came with a 
large
> supply of custom solderable coax jacks.
> 
> The datasheet is a bit skimpy and I could not link to a family spec
> anywhere. The Philips web site is IMHO not a very efficient site.
> 
> If you didn't do the layout yourself I'd take a hard look at the
> Gerber plots. More than once have I seen leftover stubs where the
> layouter wanted to go another route, decided otherwise and left a
> piece of the old trace in there. The DRC won't squawk since it's not
> connected to a third node but it adds capacitance.
> 
> Regards, Joerg
> 
> http://www.analogconsultants.com/
>