Lpc2000

I have extended and tidied up the examples I have just posted to the 
thread. I will probably post the code to the file section soon.

John Heenan

//header file interwork.h
#ifndef INTERWORK_H_
#define INTERWORK_H_

//MAKE SURE A DEFAULT ISR HANDLER IS ASSIGNED TO VICDefVectAddr
//THE DEFAULT ISR HANDLER CAN BE EMPTY BUT MUST BE PRESENT

#ifdef THUMB_INTERWORK
 #define INTDISABLE cpsr_if_disable()
 #define INTENABLE  cpsr_if_enable()
 #define SLOWINTDISABLE cpsr_i_disable()
 #define SLOWINTENABLE  cpsr_i_enable()
 //volatile definition forces stack storage and is not required
 //as optimisation sees variable is used by a function and so keeps
 #define INTVAR int cpsr_prior
 #define INTGETDISABLE cpsr_prior=cpsr_ifget_disable()
 #define INTRESTORE cpsr_c_restore(cpsr_prior)

 void cpsr_if_disable(void); //works with thumb
 void cpsr_if_enable(void);
 void cpsr_i_disable(void);
 void cpsr_i_enable(void);
 int cpsr_ifget_disable(void);
 void cpsr_c_restore(int cpsr_prior);
#else
 #define INTDISABLE INTIF_DISABLE
 #define INTENABLE  INTIF_ENABLE
 #define SLOWINTDISABLE INTI_DISABLE
 #define SLOWINTENABLE  INTI_ENABLE
 #define INTVAR volatile int cpsr_prior
 #define INTGETDISABLE INTIFGET_DISABLE(cpsr_prior)
 #define INTRESTORE INTIF_RESTORE(cpsr_prior)
#endif

/*
Usage example
  INTDISABLE
  
  INTENABLE


  INTVAR;
  INTGETDISABLE;
  
  
  INTRESTORE;
  
  INTGETDISABLE;
  
  
  INTRESTORE;
*/

//not OK for thumb code
#define INTIF_ENABLE   asm volatile ( \
   "mrs r3,cpsr     \n\t" \
   "bic r3,r3,#0xC0 \n\t" \
   "msr cpsr_c,r3   \n\t" \
   :                      \
   :                      \
   : "r3"                 \
)

#define INTIF_DISABLE  asm volatile ( \
   "mrs r3,cpsr		\n\t" \
   "orr r3,r3,#0x80 \n\t" /* I bit. separate disablement: see user 
manual */ \
   "msr cpsr_c,r3   \n\t" \
   "orr r3,r3,#0x40 \n\t" /* F bit */ \
   "msr cpsr_c,r3   \n\t" \
   :                      \
   :                      \
   : "r3"                 \
)

#define INTI_ENABLE   asm volatile ( \
   "mrs r3,cpsr     \n\t" \
   "bic r3,r3,#0x80 \n\t" \
   "msr cpsr_c,r3   \n\t" \
   :                      \
   :                      \
   : "r3"                 \
)

#define INTI_DISABLE  asm volatile ( \
   "mrs r3,cpsr     \n\t" \
   "orr r3,r3,#0x80 \n\t" \
   "msr cpsr_c,r3   \n\t" \
   :                      \
   :                      \
   : "r3"                 \
)
                	
                
#define INTIFGET_DISABLE(A) asm volatile ( \
   "mrs %0, cpsr       \n\t" \
   "orr r3, %0, #0x80  \n\t"  /* I bit. separate disablement: see 
user manual */ \
   "msr cpsr_c, r3     \n\t" \
   "orr r3, r3, #0x40  \n\t"  /* F bit */ \
   "msr cpsr_c, r3     \n\t" \
    : "=r"(A)                \
    :                        \
    : "r3"                   \
)                                         

#define INTIF_RESTORE(A) asm volatile ( \
   "msr cpsr_c, %0 \n\t" \
    :                    \
    : "r"(A)             \
)

#endif // INTERWORK_H_

//##########################

//module file interwork.c compiled as ARM assembler
#include "interwork.h"
void cpsr_if_disable(void)
{
 INTIF_DISABLE;
}

void cpsr_if_enable(void)
{
  INTIF_ENABLE;
}

void cpsr_i_disable(void)
{
  INTI_DISABLE;
}

void cpsr_i_enable(void)
{
  INTI_ENABLE;
}

int cpsr_ifget_disable(void)
{
  unsigned int cpsr_prior;
  INTIFGET_DISABLE(cpsr_prior);
  return cpsr_prior;  
//assembler generated
// mrs r0, cpsr       
// orr r3, r0, #0x80  
// msr cpsr_c, r3     
// orr r3, r3, #0x40  
// msr cpsr_c, r3     
// bx	lr
}

void cpsr_c_restore(int cpsr_prior)
{
  INTIF_RESTORE(cpsr_prior);	
//assembler generated
// msr cpsr_c, r0  
// bx	lr
}

--- In lpc2000@yahoogroups.com, "John Heenan" <l10@...> wrote:
>
> Despised by the 'beautiful people' but practical, macros make it is 
> easy to retarget ARM inline assembler to work with C code compiled 
as 
> Thumb assembler.
> 
> Following are expamples for interrupt disable/enable for GCC. The 
> intention is simply to force the macros through functions compiled 
as 
> ARM code so as the compiler will force correct usage of bx to 
switch 
> between ARM and Thumb modes, when compiling Thumb code. The beauty 
of 
> the macro system is that all ARM generated code can use pure inline 
> assembler through