Lpc2000

--- In lpc2000@yahoogroups.com, "topandurangs" <pandurang@...> wrote:
>
> 
> Hi all,
> 
>     I have few doubts on PLL.Why during enabling PLL MULTIPLIER & 
> DIVISOR both factors required.
>     By using just multiplier we can increase the processsor clock 
> frequency.
>     As i understand from the manual it may need to increase the  
> frequncy ,for the required frequency range of CCO which is quite 
> high & then reduce again upto system clock.
>    
> The PLL output frequency (when the PLL is both active and connected) 
> is given by:
> 
> eq1. CCLK = M × FOSC or CCLK = FCCO / (2 × P)
> 
> The CCO frequency can be computed as:
> 
> eq2. FCCO = CCLK × 2 × P or FCCO = FOSC × M × 2 × P
> 
>         With all this stuff i am not facing any problem but still i 
> trying to know few basic things. 
>         Can any one give me reference link where i can get more 
> information on it.
> 
> 
> Thanks & Regards,
> 
> Pandurang S.
>

Hi,
I'd suggest this article to learn some pll basics:
http://www.uoguelph.ca/~antoon/gadgets/pll/pll.html

Regards,
  Max