Lpc2000

At 03:09 PM 4/26/2006 -0700, Steve Franks wrote:
> >Well considering the 2103 claims a typical operating current on the 1V8
>supply of from 7mA to 41mA you are already in a different league.  Three
>orders of magnitude is not easily crossed.
>
>Not necissarially - the AtMega128 8-bit Avr sucks a healthy 10mA when
>operating at 8MHz.

I had misread your quiescent current as operating current.  Makes a bit of 
difference  :)

>I did the calculations and when a mote is operating (sample sensors, tx
>data) for 10mS every 60s, you have a 6000:1 duty cycle, so your 10mA looks
>like 1.6uA.  Therefore the sleep current is the dominant drain on your
>batteries.  TI's vey best LDO's eat 10uA Iq, so you're looking at two LDO's
>doubling your dominant current consumption.  Can take a mote's effective
>deployed life down accordingly.

Not quite, you still have to add your sleep current that brings you back up 
to almost 10uA again.  Your increase in Iq from the extra regulator is now 
'only' 50%.  I don't suppose any of the dual regulators help?

>I suppose the ideal solution is a discrete watchdog chip which would pull up
>the power supplies on interrupt long enough for the chip to boot.  Adds yet
>more mm-sq to your design, and I doubt very much I can find one of those to
>run at 10uA.

One of the 6 pin PICs maybe?  I haven't checked the current draw on one of 
them.

>Well, I'm out.  Maybe Philips will take notice and let VccIO go down
>to 1.8Von their next effort.  I think it's silly to run a
>3.3V rail to get a 1.8V core processor to talk to a 1.8V core FPGA which is
>another thing I do....

Now there's a matter of perspective.  I'd like to see true 5V I/O rather 
than merely 5V tolerant.  I'd like the extra noise tolerance.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,   be 
they legal, genetic, or physical.  If you don't believe me, try to chew a 
radio signal. "  -- Kelvin Throop, III
http://www.aeolusdevelopment.com/