Lpc2000

--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@...> wrote:
>
> At 09:45 PM 5/7/2006 +0000, derbaier wrote:
> >You can look up the functions of the MAMCR(0xE01FC000) and
> >MAMTIM(0xE01FC004) registers in the User Manual to see how wait states
> >are configured, but the RESET state is to have the MAM disabled. I can
> >not tell from reading the register descriptions if all 6 wait states
> >are enabled if MAMCR is all zeros, OR if there are no wait states
> >enabled if MAMCR is disabled.
> 
>  From page 83 of the user manual
> 
> MAMTIM provides 7 cycles for memory fetch on reset.
> 
> And earlier in the same section when MAMCR is 0 no memory fetches use 
> latched data, all initiate a fetch cycle.
> 
> Robert
> 
I have not used the 2129 varient for a while, so that probably
explains why that information is not on page 83 of the 3 May 2004
manual that I used. You probably have an actual current manual?
Regardless, your comment made me look a little deeper in my own manual
and I did find some similar info.  This statement on page 92 of my
manual explains how it is actually accomplished.

"The MAM actually uses latched data if it is available, but mimics the
timing of a Flash read operation. This saves power while
resulting in the same execution timing. The MAM can truly be turned
off by setting the fetch timing value in MAMTIM to one
clock."

So, to get the simulator times and the actual times to agree, he needs
to enable MAMCR and set MAMTIM for a 1 clock access?  And, of course,
run the ARM clock at less than 20MHZ.  :-)

Thanks for the setting me straight!
--Dave