Lpc2000

Hi,

I've read that other people have had problems with the WE signal on
the data bus of the LPC2214/94 (mostly regarding the RBLE bit). My
problem is however a bit different.

I'm interfacing a 16-bit wide device (EMC bank 1) and have configured
BCFG1 as follows: MW = 1, RBLE = 1, IDCY = 10, WP = 0, BM = 0.

When watching the data/address bus on a logic analyzer (write
sequence) everything looks fine:
1. The address is setup
2. CS and WE goes low
3. The data becomes valid
4. WE goes high 
5. CS goes high.
Depending on the number of wait states (WST2 in BCFGx) the timing is
affected (as expected).

However, after CS and WE have gone low (2.), WE, for some reason, goes
high for about 30 ns and then returns to low state (before going high
again (4.) before CS goes high (5.) as normal).

Anyone got any ideas why this happens?

/Anders