Lpc2000

Hi,

I've read that other people have had problems with the WE signal on
the data bus of the LPC2214/94 (mostly regarding the RBLE bit). My
problem is however a bit different.

I'm interfacing a 16-bit wide device (EMC bank 1) and have configured
BCFG1 as follows: MW = 1, RBLE = 1, IDCY = 10, WP = 0, BM = 0.

When watching the data/address bus on a logic analyzer (write
sequence) everything looks fine:
1. The address is setup
2. CS and WE goes low
3. The data becomes valid
4. WE goes high 
5. CS goes high.
Depending on the number of wait states (WST2 in BCFGx) the timing is
affected (as expected).

However, after CS and WE have gone low (2.), WE, for some reason, goes
high for about 30 ns and then returns to low state (before going high
again (4.) before CS goes high (5.) as normal).

Anyone got any ideas why this happens?

/Anders

Me again,

I figured out what was wrong with my system.
I'm interfacing a device that has 16 data lines and holds a number of
16-bit wide registers internally. These registers are supposed to be
written and read one by one.

As I had configured my uC to use 16-bit wide data bus the uC tried to
write a 32 bit word to the external device in two steps:
* First write the 16 MSBs 
* Then increment the address and 
* Finaly write the 16 LSBs. 

The solution was of course to configure the EMC to use a 32-bit wide
data bus and just ignore the 16 most significant bits of the data.

/Anders

--- In lpc2000@yahoogroups.com, "andersryl" <andersryl@...> wrote:

>
> Hi,
> 
> I've read that other people have had problems with the WE signal on
> the data bus of the LPC2214/94 (mostly regarding the RBLE bit). My
> problem is however a bit different.
> 
> I'm interfacing a 16-bit wide device (EMC bank 1) and have configured
> BCFG1 as follows: MW = 1, RBLE = 1, IDCY = 10, WP = 0, BM = 0.
> 
> When watching the data/address bus on a logic analyzer (write
> sequence) everything looks fine:
> 1. The address is setup
> 2. CS and WE goes low
> 3. The data becomes valid
> 4. WE goes high 
> 5. CS goes high.
> Depending on the number of wait states (WST2 in BCFGx) the timing is
> affected (as expected).
> 
> However, after CS and WE have gone low (2.), WE, for some reason, goes
> high for about 30 ns and then returns to low state (before going high
> again (4.) before CS goes high (5.) as normal).
> 
> Anyone got any ideas why this happens?
> 
> /Anders
>

--- In lpc2000@yahoogroups.com, "andersryl" <andersryl@...> wrote:

> The solution was of course to configure the EMC to use a 32-bit wide
> data bus and just ignore the 16 most significant bits of the data.

I would not recommend this.

I suggest you configure EMC to use it as 16-bit device, and wire the
addresss lines so that it will work correctly for both 16- and 32-bit
accesses.

You can wire up any 16-bit (or 8-bit) device to LPC such that it works
correctly for for 8- 16- and 32-bit accesses.

Jaya