I was hoping to achieve faster speeds, but since the GPIO is pretty slow and I got pretty much the same speeds as mentioned in message 37 (ie. somewhere around 150ns per bit, 300ns per cycle). I've since decided to go with a CPLD for faster clocking (ie. LPC210x writes 8 bits at a time into a CPLD which then clocks the data out faster). The bottleneck is the GPIO which seems to use many clocks to effect a write. Thus, fiddling the VPB clock changes the performance significantly but the MAM does not has as much impact. -- Charles
Message
Re: I/O bit banging speed.
2004-03-31 by embeddedjanitor