I have a problem with the startup code for the LPC2292!
My selfmade target consist of: onchip Flash; CS0:Ram 32 Bit;
CS1:Ram32Bit; CS2: Peripherals16Bit; Cs3 Display+Uart 8bit
The problem I encounter is that I can`t access external memory. The
controller doesn´t generate the strobe signals nor any addresses!
What am I doing wrong?!
My startup code:
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80
F_Bit EQU 0x40
UND_Stack_Size EQU 0x00000004
SVC_Stack_Size EQU 0x00000004
ABT_Stack_Size EQU 0x00000004
FIQ_Stack_Size EQU 0x00000004
IRQ_Stack_Size EQU 0x00000080
USR_Stack_Size EQU 0x00000400
AREA STACK, DATA, READWRITE, ALIGN=2
DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode
DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode
DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode
DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode
DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode
DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode
Top_Stack:
// Phase Locked Loop (PLL) definitions
PLL_BASE EQU 0xE01FC080 /* PLL Base Address */
PLLCON_OFS EQU 0x00 /* PLL Control Offset*/
PLLCFG_OFS EQU 0x04 /* PLL Configuration */
PLLSTAT_OFS EQU 0x08 /* PLL Status Offset */
PLLFEED_OFS EQU 0x0C /* PLL Feed Offset */
PLLCON_PLLE EQU (1<<0) /* PLL Enable */
PLLCON_PLLC EQU (1<<1) /* PLL Connect */
PLLCFG_MSEL EQU (0x1F<<0) /* PLL Multiplier */
PLLCFG_PSEL EQU (0x03<<5) /* PLL Divider */
PLLSTAT_PLOCK EQU (1<<10) /* PLL Lock Status */
// PLL Setup
PLLCFG_Val EQU 0x00000025
VPBDIV EQU 0xE01FC100
VPBDIV_Val EQU 0x11 // Memory Accelerator Module (MAM)
definitions
MAM_BASE EQU 0xE01FC000 /* MAM Base Address */
MAMCR_OFS EQU 0x00 /* MAM Control Offset*/
MAMTIM_OFS EQU 0x04 /* MAM Timing Offset */
MAMCR_Val EQU 0x00000002
MAMTIM_Val EQU 0x00000004
// External Memory Controller (EMC) definitions
EMC_BASE EQU 0xFFE00000 /* EMC Base Address */
BCFG0_OFS EQU 0x00 /* BCFG0 Offset */
BCFG1_OFS EQU 0x04 /* BCFG1 Offset */
BCFG2_OFS EQU 0x08 /* BCFG2 Offset */
BCFG3_OFS EQU 0x0C /* BCFG3 Offset */
// Bank Configuration BCFG 0 - 3
BCFG0_Val EQU 0x2000FFEF
BCFG1_Val EQU 0x2000FFEF
BCFG2_Val EQU 0x1000FBEF
BCFG3_Val EQU 0x0000FBEF
PCONP EQU 0xE01FC0C4
PCONP_Val EQU 0x00000002
// External Memory Pins definitions
IO0DIR EQU 0xE0028008
IO0DIR_Val EQU 0x2BFE0331
IO1DIR EQU 0xE0028018
IO1DIR_Val EQU 0x00000003
IO2DIR EQU 0xE0028028
IO2DIR_Val EQU 0xFFFFFFFF
IO3DIR EQU 0xE0028038
IO3DIR_Val EQU 0xFFFFFFFF
PINSEL0 EQU 0xE002C000
PINSEL0_Val EQU 0x00000000
PINSEL1 EQU 0xE002C004
PINSEL1_Val EQU 0x00000000
PINSEL2 EQU 0xE002C014
PINSEL2_Val EQU 0xD816924
CODE_BASE EQU 0x00000000 // internal Flash
AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4
PUBLIC __startup
EXTERN CODE32 (?C?INIT)
__startup PROC CODE32
EXTERN CODE32 (Undef_Handler?A)
EXTERN CODE32 (SWI_Handler?A)
EXTERN CODE32 (PAbt_Handler?A)
EXTERN CODE32 (DAbt_Handler?A)
EXTERN CODE32 (IRQ_Handler?A)
EXTERN CODE32 (FIQ_Handler?A)
Vectors: LDR PC,Reset_Addr
LDR PC,Undef_Addr
LDR PC,SWI_Addr
LDR PC,PAbt_Addr
LDR PC,DAbt_Addr
NOP /* Reserved Vector */
; LDR PC,IRQ_Addr
LDR PC,[PC, #-0x0FF0] /* Vector from
VicVectAddr */
LDR PC,FIQ_Addr
Reset_Addr: DD Reset_Handler
Undef_Addr: DD Undef_Handler?A
SWI_Addr: DD SWI_Handler?A
PAbt_Addr: DD PAbt_Handler?A
DAbt_Addr: DD DAbt_Handler?A
DD 0 /* Reserved Address */
IRQ_Addr: DD IRQ_Handler?A
FIQ_Addr: DD FIQ_Handler?A
//ORG CODE_BASE + 0x40 // Interruptvektoren schützen
// Reset Handler
Reset_Handler:
LDR R0, =PCONP
LDR R1, =PCONP_Val
STR R1, [R0]
LDR R0, =IO0DIR
LDR R1, =IO0DIR_Val
STR R1, [R0]
LDR R0, =IO1DIR
LDR R1, =IO1DIR_Val
STR R1, [R0]
LDR R0, =IO2DIR
LDR R1, =IO2DIR_Val
STR R1, [R0]
LDR R0, =IO3DIR
LDR R1, =IO3DIR_Val
STR R1, [R0]
LDR R0, =PINSEL0
LDR R1, =PINSEL0_Val
STR R1, [R0]
LDR R0, =PINSEL1
LDR R1, =PINSEL1_Val
STR R1, [R0]
LDR R0, =PINSEL2
LDR R1, =PINSEL2_Val
STR R1, [R0]
LDR R0, =VPBDIV
LDR R1, =VPBDIV_Val
STR R1, [R0]
LDR R0, =EMC_BASE
LDR R1, =BCFG0_Val
STR R1, [R0, #BCFG0_OFS]
LDR R1, =BCFG1_Val
STR R1, [R0, #BCFG1_OFS]
LDR R1, =BCFG2_Val
STR R1, [R0, #BCFG2_OFS]
LDR R1, =BCFG3_Val
STR R1, [R0, #BCFG3_OFS]
LDR R0, =PLL_BASE
MOV R1, #0xAA
MOV R2, #0x55
// Configure and Enable PLL
MOV R3, #PLLCFG_Val
STR R3, [R0, #PLLCFG_OFS]
MOV R3, #PLLCON_PLLE
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
// Wait until PLL Locked
PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS]
ANDS R3, R3, #PLLSTAT_PLOCK
BEQ PLL_Loop
// Switch to PLL Clock
MOV R3, #(PLLCON_PLLE | PLLCON_PLLC)
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
LDR R0, =MAM_BASE
MOV R1, #MAMTIM_Val
STR R1, [R0, #MAMTIM_OFS]
MOV R1, #MAMCR_Val
STR R1, [R0, #MAMCR_OFS]
// Memory Mapping (when Interrupt Vectors are in RAM)
MEMMAP EQU 0xE01FC040 /* Memory Mapping Control */
LDR R0, =MEMMAP
MOV R1, #1
STR R1, [R0]
// Setup Stack for each mode
LDR R0, =Top_Stack
// Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
// Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
// Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
// Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
// Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
// Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
MOV SP, R0
// Enter the C code
LDR R0,=?C?INIT
TST R0,#1 ; Bit-0 set: main is Thumb
LDREQ LR,=exit?A ; ARM Mode
LDRNE LR,=exit?T ; Thumb Mode
BX R0
ENDP
PUBLIC exit?A
exit?A PROC CODE32
B exit?A
ENDP
PUBLIC exit?T
exit?T PROC CODE16
exit: B exit?T
ENDP
ENDMessage
LPC2292 startup code wrong?
2006-05-30 by frank_gruber11