Lpc2000

I have been reading the errata and many of the messages on this board 
and still cannot find out what is going on.

I have a PWM match interrupt (FIQ) that happens about every 300 system 
clock cycles or 5uS. The ISR takes about 2.2uS as indicated by the 
GPIO that is high during the ISR. I set a test at the beginning of the 
ISR to look at another timer value and if it has be greater than 400 
clocks set another GPIO. This indicates that I missed an interrupt.

When I look at the scope I see two different conditions. First, I 
usually see a gap in the interrupt indicator just before the missing 
interrupt indicator. All interrupts before and after this gap are 
properly timed. There are no overlaps of interrupts. There are no 
other interrupts firing at this time. If this were a latency issue, I 
would expect to see the interrupt enter late and overlap the next 
interrupt. Any clues?

The second condition is that the test if(!(PWMIR & 0x01)) indicates 
that it entered the interrupt without knowing why, but it does enter 
the interrupt with the proper timing, exactly as if it were the PWMIR 
interrupt.

The missing interrup causes the PWM to cycle 1 time too many messing 
up some critical timing. Any help is appreciated.