Lpc2000

At 12:04 AM 4/19/04 +0000, you wrote:
>--- In lpc2000@yahoogroups.com, "nw_mcu" <nw_mcu@y...> wrote:
>
>OK, I've now confirmed the PLL problem! With my 2106, I get the
>following results:
>
>PLL OFF: 1150ns (14.7Mhz)
>PLLCFG = 0x61 (P=3, M=1): 577ns (should be 14.7Mhz but is 29Mhz)

Ah, I see what's happening,  I should have clued in earlier

PlLLCFG of 61 gives PSEL of 3, MSEL of 1

That gives a P of 8 and and M of 2

In turn Fcco is 470MHz (outside the valid range) and cclk is 29.4 MHz

If you check http://www.aeolusdevelopment.com the newlib-lpc source has an 
example of how to set up the PLL.

Robert



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