Lpc2000

Spurious interrupts are a result of the asynchonous nature of 
interrupt handling. The asynchronous nature is caused by the delay 
between when the core detects an interrupt and when it processes the 
interrupt, and the VIC state changing during that period. ie 
something like:

1) VIC decides there is an interrupt and sends the NIRQ signal to the 
core.
2) Core latches the NIRQ state.
3) Processing continues for a few cycles due to pipelining.
4) Core loads IRQ address from VIC.

Now if the VIC state changes during step 3 (eg due to the VIC being 
modified so that the interrupt that triggered is no longer pending 
[eg. the interrupt got disabled]) then in step 4 the VIC says "What 
interrupt?". In this case, the VIC returns the default interrupt 
VicDefVectAddr (0xFFFFF034). If this is not set up properly then 
things go silly.

There are two things you can do here:
1. Set things up so that the spurious interrupts never happen. Just 
guarding changes to the VIC might not be enough since glitches on 
level sensitive interrupts can also cause spurious interrupts (well 
in some parts anyway).

2. Set up a VIC default handler and test it properly.

-- Charles

--- In lpc2000@yahoogroups.com, "the ARM Patch" <thearmpatch@c...> 
wrote:
> I'll hop in here for a second.  As an added note, I believe 
changing the
> VIC as the original post stated, will just un-vector the 
interrupt.  I
> would suggest the following sequence.
> 1) disable global IRQ
> 2) disable/enable external interrupt (you may need to do this by 
changing
>    the pin to a GPIO input in the appropriate PINSEL register.  
GURUs jump
>    in here.)
> 3) enable global IRQ
> 
> Regards
> -Bill Knight
> R O SoftWare