Lpc2000

> 1) VIC decides there is an interrupt and sends the NIRQ signal to the 
> core.
> 2) Core latches the NIRQ state.
> 3) Processing continues for a few cycles due to pipelining.
> 4) Core loads IRQ address from VIC.

So, you're saying the VIC is BAD--Broken As Designed.  There should
be a latch *in the CPU core* that holds the vector when the NIRQ
is asserted and an acknowledge to clear the VIC.

Yes, yes, I know, one can live with this, but it's more in the realm
of "documented bugs are features" rather than something one would
actually want to work this way.

I take it this came from the ARM2/3 days when there was one physical
IRQ to the CPU and a peripherial handled combining IRQs?

Cheers,
David