Lpc2000

Art Sobel wrote:

> You'd think that but i did put an 8 into the counter and all I got was
> 12,000 samples a sec. I programmed the port as master but the SSCS is
> never generated.

SSCS is actually always an input to the LPC21XX... it is used by some 
external SPI master to select the LPC21XX spi hardware as the target 
slave.  So if it's not de-asserted for the duration of SPI transfers 
originating from the LPC21XX, you get what they call a mode fault. 
That's why it's safe to simply pull it high via a resistor if the 
LPC21XX will never be a SPI slave.

As for the clocking... do you have the PLL set up to run CCLK at 60 MHz? 
  Do you have the PCLK divider set to 1 (I think it defaults to 4)?  You 
might also check the SPICLK period... 12,500 sixteen-bit samples per 
second would imply that you're only running the SPI at 200 KHz, or a 
PCLK of 1.6 MHz with SPCCR=8.  You can definitely get much faster than that.

Of course the delay could be coming from something besides the SPI 
hardware (i.e. the software...).  This would show up if you see a fast 
SPICLK, but long durations between samples.

Ryan