Lpc2000

In the process of attaching some SPI peripherals to the chip I ran
into some strange  behaviour.  There are 4 pins to use, SPICLK, MISO,
MOSI and SSCS, First the SSCS pin must be configured as an SPI PIN or
the other parts of the SPI don't work at all, Next the SSCS signal is
not generated, This means that I must use another GPIO as the CS
signal. So now it uses 5 pins - with one more GPIO pin for every SPI
peripheral. 

Using the fastest selection of clocks the output rate is about 12,500
D/A samples a second (each D/A sample requires 2 bytes of data
output). This just about scratches the idea that the chip could
produce medium quality sound output. One channel just barely then if
you want to have analog in on the SPI too then the throughput just
dives. How the heck did they ever think this chip could do modems?

Sobellinni

Art Sobel wrote:

> In the process of attaching some SPI peripherals to the chip I ran
> into some strange  behaviour.  There are 4 pins to use, SPICLK, MISO,
> MOSI and SSCS, First the SSCS pin must be configured as an SPI PIN or
> the other parts of the SPI don't work at all, Next the SSCS signal is
> not generated, This means that I must use another GPIO as the CS
> signal. So now it uses 5 pins - with one more GPIO pin for every SPI
> peripheral. 
> 
> Using the fastest selection of clocks the output rate is about 12,500
> D/A samples a second (each D/A sample requires 2 bytes of data
> output). This just about scratches the idea that the chip could
> produce medium quality sound output. One channel just barely then if
> you want to have analog in on the SPI too then the throughput just
> dives. How the heck did they ever think this chip could do modems?

A couple of thoughts:

  - If the 21XX is always only going to serve as SPI master
    (i.e. it will never be selected as a SPI slave), then
    it makes sense to use a pullup on SSCS.
  - Not sure I follow your throughput math.  The max PCLK
    rate is 60 MHz (divide by 1 with a 60 MHz CCLK).  The
    max SPI clock is PCLK / 8, or 7.5 MHz.  At 7.5 MHz
    2 bytes should take 2.13 usec (468,750 samples/sec), no?

Ryan

--- In lpc2000@yahoogroups.com, MaxStream - Ryan Bedwell <ryanb@m...>
wrote:
> Art Sobel wrote:
> 
> > In the process of attaching some SPI peripherals to the chip I ran
> > into some strange  behaviour.  There are 4 pins to use, SPICLK, MISO,
> > MOSI and SSCS, First the SSCS pin must be configured as an SPI PIN or
> > the other parts of the SPI don't work at all, Next the SSCS signal is
> > not generated, This means that I must use another GPIO as the CS
> > signal. So now it uses 5 pins - with one more GPIO pin for every SPI
> > peripheral. 
> > 
> > Using the fastest selection of clocks the output rate is about 12,500
> > D/A samples a second (each D/A sample requires 2 bytes of data
> > output). This just about scratches the idea that the chip could
> > produce medium quality sound output. One channel just barely then if
> > you want to have analog in on the SPI too then the throughput just
> > dives. How the heck did they ever think this chip could do modems?
> 
> A couple of thoughts:
> 
>   - If the 21XX is always only going to serve as SPI master
>     (i.e. it will never be selected as a SPI slave), then
>     it makes sense to use a pullup on SSCS.
>   - Not sure I follow your throughput math.  The max PCLK
>     rate is 60 MHz (divide by 1 with a 60 MHz CCLK).  The
>     max SPI clock is PCLK / 8, or 7.5 MHz.  At 7.5 MHz
>     2 bytes should take 2.13 usec (468,750 samples/sec), no?
> 
> Ryan

You'd think that but i did put an 8 into the counter and all I got was
12,000 samples a sec. I programmed the port as master but the SSCS is
never generated.

Art Sobel wrote:

> You'd think that but i did put an 8 into the counter and all I got was
> 12,000 samples a sec. I programmed the port as master but the SSCS is
> never generated.

SSCS is actually always an input to the LPC21XX... it is used by some 
external SPI master to select the LPC21XX spi hardware as the target 
slave.  So if it's not de-asserted for the duration of SPI transfers 
originating from the LPC21XX, you get what they call a mode fault. 
That's why it's safe to simply pull it high via a resistor if the 
LPC21XX will never be a SPI slave.

As for the clocking... do you have the PLL set up to run CCLK at 60 MHz? 
  Do you have the PCLK divider set to 1 (I think it defaults to 4)?  You 
might also check the SPICLK period... 12,500 sixteen-bit samples per 
second would imply that you're only running the SPI at 200 KHz, or a 
PCLK of 1.6 MHz with SPCCR=8.  You can definitely get much faster than that.

Of course the delay could be coming from something besides the SPI 
hardware (i.e. the software...).  This would show up if you see a fast 
SPICLK, but long durations between samples.

Ryan

Art Sobel wrote:
> In the process of attaching some SPI peripherals to the chip I ran
> into some strange  behaviour.  There are 4 pins to use, SPICLK, 
MISO,
> MOSI and SSCS, First the SSCS pin must be configured as an SPI PIN 
or
> the other parts of the SPI don't work at all, Next the SSCS signal 
is
> not generated, This means that I must use another GPIO as the CS
> signal. So now it uses 5 pins ......

Maybe I misunderstand, but do you really mean that the pin 
configured as SSCS does not produce any CS signal?  So it's just 
useless, and you have to use yet another pin for this?  

I'm designing a circuit that will use SPI, and I was assuming I 
could use the SSCS for chip select.

- Chris Graham

if you are using spi as master then SSCS cannot be
used to select slave devices ,you have to use one of
the gpio for selecting slave device

but never forget to tie SSCS To tie to Vcc in spi 
master mode

SSCS is to select LPc device as slave by an other spi
device,but not to generate any signal,

thanks 
shridhar
--- Chris <chris_e_gr@...> wrote:
> Art Sobel wrote:
> > In the process of attaching some SPI peripherals
> to the chip I ran
> > into some strange  behaviour.  There are 4 pins to
> use, SPICLK, 
> MISO,
> > MOSI and SSCS, First the SSCS pin must be
> configured as an SPI PIN 
> or
> > the other parts of the SPI don't work at all, Next
> the SSCS signal 
> is
> > not generated, This means that I must use another
> GPIO as the CS
> > signal. So now it uses 5 pins ......
> 
> Maybe I misunderstand, but do you really mean that
> the pin 
> configured as SSCS does not produce any CS signal? 
> So it's just 
> useless, and you have to use yet another pin for
> this?  
> 
> I'm designing a circuit that will use SPI, and I was
> assuming I 
> could use the SSCS for chip select.
> 
> - Chris Graham
> 
> 



	
		
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