Lpc2000

Some follow up questions? 
 
1) Have you tried the timer interupt at the IRQ levels?
2) Why do you use the  "else if" condition. As compare to going and possible servicing all of them at same time e.g.. 
 
     ir = T0->IR;
     
     if (ir & 0x01) {
            
     }
 
     if (ir & 0x08) {
 
    }
 
Any reason?
 
Karl Olsen <kro@...> wrote:
--- In lpc2000@yahoogroups.com, h s <h7242004@y...> wrote:
> Has any one been able to successfully run all 4-compare channels of 
timer0 simultaneously (in the match interrupt mode, while the main 
timer0 is free running)? 
> The mode of operations could be such that one match channel is 
reloaded at a period rate. The other channels may be started and 
stopped as needed.  
>  
> I am losing match interrupts. 

I am using the four match interrupts and two capture interrupts on 
the free-running timer 0 in a LPC2114.  It seems to work.
In each of the two cature interrupts, I calculate two times (MRx 
values) where the match interrupts should be called, and enable the 
match interrupts:


void FIQ_Handler (void) __attribute__ ((interrupt("FIQ")));
void FIQ_Handler (void)
{
  int now;
  int ir;

  ir = T0->IR;
  if (ir & 0x01)
  {
    /* Match 0 event */
    /* ... */
    T0->MCR &= ~0x0001;  /* Disable MR0 interrupt */
    T0->IR = 0x01;
  }
  else if (ir & 0x02)
  {
    /* Match 1 event */
    /* ... */
    T0->MCR &= ~0x0008;  /* Disable MR1 interrupt */
    T0->IR = 0x02;
  }
  else if (ir & 0x04)
  {
    /* Match 2 event */
    /* ... */
    T0->MCR &= ~0x0040;  /* Disable MR2 interrupt */
    T0->IR = 0x04;
  }
  else if (ir & 0x08)
  {
    /* Match 3 event */
    /* ... */
    T0->MCR &= ~0x0200;  /* Disable MR3 interrupt */
    T0->IR = 0x08;
  }
  else if (ir & 0x10)
  {
    /* Capture 0 event */
    now = T0->CR0;
    T0->MR0 = now + ...;
    T0->MR2 = now + ...;
    T0->MCR |= 0x0041;  /* Enable MR0 and MR2 interrupts */
    T0->IR = 0x10;
  }
  else if (ir & 0x20)
  {
    /* Capture 1 event */
    now = T0->CR1;
    T0->MR1 = now + ...;
    T0->MR3 = now + ...;
    T0->MCR |= 0x0208;  /* Enable MR1 and MR3 interrupts */
    T0->IR = 0x20;
  }
}



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