Lpc2000

--- In lpc2000@yahoogroups.com, "bobbruce000" <bobbruce000@y...> 
wrote:
>> 
> > See "USAGE NOTES ON WATCHDOG RESET AND EXTERNAL START" on page 214
> > of the 2124 User Manual (Dated May 03, 2004). Does this solve your
> > problem.
> 
> No.  This note only applies to LPC2212/2214.  I am using a LPC2124.
 

On the LPC2124, you still need to be sure you have proper levels on 
P0.14, P1.20, and P1.26.  I assume they are sampled on a watchdog 
reset, just like on an external reset.  (If anyone can definitely 
confirm this, that would be appreciated.)


> Btw, I only saw this problem on one board, and no one else was able
> to reproduce the problem.  So it might have just been a bad chip or
> a bad board.  I never tested for the problem on any other board.  I
> can do some more testing if you are interested, since I now have
> some new boards.

I have come to the conclusion that the internal watchdog cannot be 
relied upon; if watchdog protection is needed - one must use an 
external watchdog.  Therefore, as far as I am concerned, any further 
testing would be of purely academic interest.

As others have noted, in addition to the processor always starting up 
with reset disabled, there is no protection for over-writing the WDTC 
register.  Writing 0xFFFFFFFF to this register would give a watchdog 
time greater than 19 minutes for a typical 14.7456 MHz pclk - 
vitually worthless.

I don't understand why Philips bothered to protect the WDEN and 
WDRESET bits without protecting the WDTC register!