Lpc2000

Leighton,

> Ok then...forgot about the divider value. Well, I tried out what u said too. I expect it to work but apparently the PLL's still
not locking...Any ideas?
>
> > Your setting of PLLCFG would cause it to run at 4*14.7456MHz * 2 * 1 == 117.96MHz,
> > just outside the allowed range. Set P to 2 and you should be ok => PLLCFG = 0x23.
> >
<snip>
> > PLLFEED = 0xAA;
> > PLLFEED = 0x55;
<snip>

the only thing left I can think of is, that the feed sequence doesn't do what it should.
Do you have interrupts enabled during the above?

-wue