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PLL not locking

PLL not locking

2004-08-24 by Leighton Rowe

I'm working on a custom 2114 board (using a 14.7456 MHz crystal) and 
I'm noticing something weird going on with the PLL.

PLLCFG = 0x03;                  //PLL Multiplier = 4 (58.98 MHz0
PLLCON = 1;                     // PLL Enable

PLLFEED = 0xAA;
PLLFEED = 0x55;                         

while(!(PLLSTAT & 0x0400));     //Wait until PLL is locked
  
PLLCON = 3;                           // Connect PLL clock
PLLFEED = 0xAA;                         
PLLFEED = 0x55;  

Apparently the PLL isn't locking, causing the processor to basically 
wait forever. 

This code works fine with the mcb2100 @ 12.Mhz (Multiplier = 5). But 
I have no clue as to why the the PLL isn't locking @ 14.74 MHz after 
I set up the registers. 

Anyone worked on this before. Your help is needed. Thanks.

Leighton

Re: [lpc2000] PLL not locking

2004-08-24 by Uwe Arends

Leighton,

from the user manual, the CCO clock has to be in the range from 156 to 320MHz.
It is calculated as M*Fosc * 2 * P with M being PLLCFG[4:0] + 1 and P being
one of 1, 2, 4, 8 for the four different values possible for PLLCFG[6:5].

Your setting of PLLCFG would cause it to run at 4*14.7456MHz * 2 * 1 == 117.96MHz,
just outside the allowed range. Set P to 2 and you should be ok => PLLCFG = 0x23.

hth
-uwe
----- Original Message ----- 
Show quoted textHide quoted text
From: "Leighton Rowe" <leightonsrowe@...>
To: <lpc2000@yahoogroups.com>
Sent: Tuesday, August 24, 2004 10:54 PM
Subject: [lpc2000] PLL not locking


> I'm working on a custom 2114 board (using a 14.7456 MHz crystal) and 
> I'm noticing something weird going on with the PLL.
> 
> PLLCFG = 0x03;                  //PLL Multiplier = 4 (58.98 MHz0
> PLLCON = 1;                     // PLL Enable
> 
> PLLFEED = 0xAA;
> PLLFEED = 0x55;                         
> 
> while(!(PLLSTAT & 0x0400));     //Wait until PLL is locked
>   
> PLLCON = 3;                           // Connect PLL clock
> PLLFEED = 0xAA;                         
> PLLFEED = 0x55;  
> 
> Apparently the PLL isn't locking, causing the processor to basically 
> wait forever. 
> 
> This code works fine with the mcb2100 @ 12.Mhz (Multiplier = 5). But 
> I have no clue as to why the the PLL isn't locking @ 14.74 MHz after 
> I set up the registers. 
> 
> Anyone worked on this before. Your help is needed. Thanks.
> 
> Leighton
> 
> 
> 
> 
> 
> 
> 
> 
>  
> Yahoo! Groups Links
> 
> 
> 
>  
> 
>

Re: [lpc2000] PLL not locking

2004-08-24 by Leighton Rowe

Ok then...forgot about the divider value. Well, I tried out what u said too. I expect it to work but apparently the PLL's still not locking...Any ideas?
 
Uwe Arends <Uwe_Arends@...> wrote:
Leighton,

from the user manual, the CCO clock has to be in the range from 156 to 320MHz.
It is calculated as M*Fosc * 2 * P with M being PLLCFG[4:0] + 1 and P being
one of 1, 2, 4, 8 for the four different values possible for PLLCFG[6:5].

Your setting of PLLCFG would cause it to run at 4*14.7456MHz * 2 * 1 == 117.96MHz,
just outside the allowed range. Set P to 2 and you should be ok => PLLCFG = 0x23.

hth
-uwe
Show quoted textHide quoted text
----- Original Message ----- 
From: "Leighton Rowe" <leightonsrowe@...>
To: <lpc2000@yahoogroups.com>
Sent: Tuesday, August 24, 2004 10:54 PM
Subject: [lpc2000] PLL not locking


> I'm working on a custom 2114 board (using a 14.7456 MHz crystal) and 
> I'm noticing something weird going on with the PLL.
> 
> PLLCFG = 0x03;                  //PLL Multiplier = 4 (58.98 MHz0
> PLLCON = 1;                     // PLL Enable
> 
> PLLFEED = 0xAA;
> PLLFEED = 0x55;                         
> 
> while(!(PLLSTAT & 0x0400));     //Wait until PLL is locked
>   
> PLLCON = 3;                           // Connect PLL clock
> PLLFEED = 0xAA;                         
> PLLFEED = 0x55;  
> 
> Apparently the PLL isn't locking, causing the processor to basically 
> wait forever. 
> 
> This code works fine with the mcb2100 @ 12.Mhz (Multiplier = 5). But 
> I have no clue as to why the the PLL isn't locking @ 14.74 MHz after 
> I set up the registers. 
> 
> Anyone worked on this before. Your help is needed. Thanks.
> 
> Leighton
> 
> 
> 
> 
> 
> 
> 
> 
>  
> Yahoo! Groups Links
> 
> 
> 
>  
> 
> 


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Re: [lpc2000] PLL not locking

2004-08-25 by Uwe Arends

Leighton,

> Ok then...forgot about the divider value. Well, I tried out what u said too. I expect it to work but apparently the PLL's still
not locking...Any ideas?
>
> > Your setting of PLLCFG would cause it to run at 4*14.7456MHz * 2 * 1 == 117.96MHz,
> > just outside the allowed range. Set P to 2 and you should be ok => PLLCFG = 0x23.
> >
<snip>
> > PLLFEED = 0xAA;
> > PLLFEED = 0x55;
<snip>

the only thing left I can think of is, that the feed sequence doesn't do what it should.
Do you have interrupts enabled during the above?

-wue

Re: PLL not locking

2004-08-25 by Leighton Rowe

All The IRQ/FIQ interrupts are disabled.

If I slowly step through with the debugger the PLLSTAT register 
doesn't even change after the feed sequence

PLLSTAT shows 0

And if I just let it run, it will still be stuck in the wait for 
lock loop...

PLLSTAT shows 0x0123 

...so the PLL's enabled but not locked

My only guess is the board wasn't connected up as it should be. 
Since the code is executing, the crystal seems to be ok but right 
now, it's made not to carry a Reset button.

Leighton

--- In lpc2000@yahoogroups.com, "Uwe Arends" <Uwe_Arends@o...> wrote:
> Leighton,
> 
> > Ok then...forgot about the divider value. Well, I tried out what 
u said too. I expect it to work but apparently the PLL's still
> not locking...Any ideas?
> >
> > > Your setting of PLLCFG would cause it to run at 4*14.7456MHz * 
2 * 1 == 117.96MHz,
> > > just outside the allowed range. Set P to 2 and you should be 
ok => PLLCFG = 0x23.
> > >
> <snip>
> > > PLLFEED = 0xAA;
> > > PLLFEED = 0x55;
> <snip>
> 
> the only thing left I can think of is, that the feed sequence 
doesn't do what it should.
Show quoted textHide quoted text
> Do you have interrupts enabled during the above?
> 
> -wue

Re: [lpc2000] Re: PLL not locking

2004-08-25 by capiman@t-online.de

Have you set PLLCFG = 0x23 (instead of 0x03 in your original sample) ?

Regards,

        Martin

----- Original Message ----- 
Show quoted textHide quoted text
From: "Leighton Rowe" <leightonsrowe@...>
To: <lpc2000@yahoogroups.com>
Sent: Wednesday, August 25, 2004 3:52 PM
Subject: [lpc2000] Re: PLL not locking


> All The IRQ/FIQ interrupts are disabled.
> 
> If I slowly step through with the debugger the PLLSTAT register 
> doesn't even change after the feed sequence
> 
> PLLSTAT shows 0
> 
> And if I just let it run, it will still be stuck in the wait for 
> lock loop...
> 
> PLLSTAT shows 0x0123 
> 
> ...so the PLL's enabled but not locked
> 
> My only guess is the board wasn't connected up as it should be. 
> Since the code is executing, the crystal seems to be ok but right 
> now, it's made not to carry a Reset button.
> 
> Leighton
> 
> --- In lpc2000@yahoogroups.com, "Uwe Arends" <Uwe_Arends@o...> wrote:
>> Leighton,
>> 
>> > Ok then...forgot about the divider value. Well, I tried out what 
> u said too. I expect it to work but apparently the PLL's still
>> not locking...Any ideas?
>> >
>> > > Your setting of PLLCFG would cause it to run at 4*14.7456MHz * 
> 2 * 1 == 117.96MHz,
>> > > just outside the allowed range. Set P to 2 and you should be 
> ok => PLLCFG = 0x23.
>> > >
>> <snip>
>> > > PLLFEED = 0xAA;
>> > > PLLFEED = 0x55;
>> <snip>
>> 
>> the only thing left I can think of is, that the feed sequence 
> doesn't do what it should.
>> Do you have interrupts enabled during the above?
>> 
>> -wue
> 
> 
> 
> 
> 
> Yahoo! Groups Links
> 
> 
> 
> 
>

Re: PLL not locking

2004-08-25 by Leighton Rowe

Yep. PLLCFG's set to 0x23.

--- In lpc2000@yahoogroups.com, capiman@t... wrote:
> Have you set PLLCFG = 0x23 (instead of 0x03 in your original 
sample) ?
> 
> Regards,
> 
>         Martin
> 
> ----- Original Message ----- 
> From: "Leighton Rowe" <leightonsrowe@y...>
> To: <lpc2000@yahoogroups.com>
> Sent: Wednesday, August 25, 2004 3:52 PM
> Subject: [lpc2000] Re: PLL not locking
> 
> 
> > All The IRQ/FIQ interrupts are disabled.
> > 
> > If I slowly step through with the debugger the PLLSTAT register 
> > doesn't even change after the feed sequence
> > 
> > PLLSTAT shows 0
> > 
> > And if I just let it run, it will still be stuck in the wait for 
> > lock loop...
> > 
> > PLLSTAT shows 0x0123 
> > 
> > ...so the PLL's enabled but not locked
> > 
> > My only guess is the board wasn't connected up as it should be. 
> > Since the code is executing, the crystal seems to be ok but 
right 
> > now, it's made not to carry a Reset button.
> > 
> > Leighton
> > 
> > --- In lpc2000@yahoogroups.com, "Uwe Arends" <Uwe_Arends@o...> 
wrote:
> >> Leighton,
> >> 
> >> > Ok then...forgot about the divider value. Well, I tried out 
what 
> > u said too. I expect it to work but apparently the PLL's still
> >> not locking...Any ideas?
> >> >
> >> > > Your setting of PLLCFG would cause it to run at 
4*14.7456MHz * 
> > 2 * 1 == 117.96MHz,
> >> > > just outside the allowed range. Set P to 2 and you should 
be 
Show quoted textHide quoted text
> > ok => PLLCFG = 0x23.
> >> > >
> >> <snip>
> >> > > PLLFEED = 0xAA;
> >> > > PLLFEED = 0x55;
> >> <snip>
> >> 
> >> the only thing left I can think of is, that the feed sequence 
> > doesn't do what it should.
> >> Do you have interrupts enabled during the above?
> >> 
> >> -wue
> > 
> > 
> > 
> > 
> > 
> > Yahoo! Groups Links
> > 
> > 
> > 
> > 
> >

PLL Calculator

2004-08-25 by Richard

In the ineterest of learning Visual Basic I have created a PLL 
Calulator application.  Please check it out and let me know of errors 
or needed improvements.

Richard

http://f6.grp.yahoofs.com/v1/gLcsQY9uIEwnJWvckxURs-
ePoupA_QP15YeBrAAAfGA7g1fOPlytFjqLelO_9FJ90kP4nhn5gQJmIqoXGRpyWK5LI9mu
/PLL_calculator.zip

Re: [lpc2000] PLL Calculator

2004-08-25 by capiman@t-online.de

Hello Richard,

here the results of a short test:

1) Installer wants to install in directory ...\project1 or so. Perhaps 
choose there "PLL_Calculator" or something else
2) When i start it, start up values are invalid. Perhaps better choose a 
valid value like P=2
3) Entering M = 0 or big (or too big number) result in multibyte PLLCFG
4) Can you implement something like a "suggest" button. You enter the Fosc 
and program suggest valid P / M to get highest performance ?

Regards,

          Martin

----- Original Message ----- 
Show quoted textHide quoted text
From: "Richard" <richas@...>
To: <lpc2000@yahoogroups.com>
Sent: Wednesday, August 25, 2004 6:50 PM
Subject: [lpc2000] PLL Calculator


> In the ineterest of learning Visual Basic I have created a PLL
> Calulator application.  Please check it out and let me know of errors
> or needed improvements.
>
> Richard
>
> http://f6.grp.yahoofs.com/v1/gLcsQY9uIEwnJWvckxURs-
> ePoupA_QP15YeBrAAAfGA7g1fOPlytFjqLelO_9FJ90kP4nhn5gQJmIqoXGRpyWK5LI9mu
> /PLL_calculator.zip
>
>
>
>
>
> Yahoo! Groups Links
>
>
>
>
>

Re: PLL Calculator

2004-08-25 by Richard

Thanks for the feedback, see below.

Richard

--- In lpc2000@yahoogroups.com, capiman@t... wrote:
> Hello Richard,
> 
> here the results of a short test:
> 
> 1) Installer wants to install in directory ...\project1 or so. 
Perhaps 
> choose there "PLL_Calculator" or something else
OK

> 2) When i start it, start up values are invalid. Perhaps better 
choose a 
> valid value like P=2
OK, will do.

> 3) Entering M = 0 or big (or too big number) result in multibyte 
PLLCFG
Yes, very wrong, will fix that.

> 4) Can you implement something like a "suggest" button. You enter 
the Fosc 
> and program suggest valid P / M to get highest performance ?
Hmmm, maybe.

> 
> Regards,
> 
>           Martin
> 
> ----- Original Message ----- 
> From: "Richard" <richas@y...>
> To: <lpc2000@yahoogroups.com>
> Sent: Wednesday, August 25, 2004 6:50 PM
> Subject: [lpc2000] PLL Calculator
> 
> 
> > In the ineterest of learning Visual Basic I have created a PLL
> > Calulator application.  Please check it out and let me know of 
errors
> > or needed improvements.
> >
> > Richard
> >
> > http://f6.grp.yahoofs.com/v1/gLcsQY9uIEwnJWvckxURs-
> > 
ePoupA_QP15YeBrAAAfGA7g1fOPlytFjqLelO_9FJ90kP4nhn5gQJmIqoXGRpyWK5LI9mu
Show quoted textHide quoted text
> > /PLL_calculator.zip
> >
> >
> >
> >
> >
> > Yahoo! Groups Links
> >
> >
> >
> >
> >

Re: PLL Calculator

2004-08-25 by Richard

OK, try it now.  I have (hopefully) fixed the PLLCFG and initial 
value issues.

Richard

--- In lpc2000@yahoogroups.com, capiman@t... wrote:
> Hello Richard,
> 
> here the results of a short test:
> 
> 1) Installer wants to install in directory ...\project1 or so. 
Perhaps 
> choose there "PLL_Calculator" or something else
> 2) When i start it, start up values are invalid. Perhaps better 
choose a 
> valid value like P=2
> 3) Entering M = 0 or big (or too big number) result in multibyte 
PLLCFG
> 4) Can you implement something like a "suggest" button. You enter 
the Fosc 
> and program suggest valid P / M to get highest performance ?
> 
> Regards,
> 
>           Martin
> 
> ----- Original Message ----- 
> From: "Richard" <richas@y...>
> To: <lpc2000@yahoogroups.com>
> Sent: Wednesday, August 25, 2004 6:50 PM
> Subject: [lpc2000] PLL Calculator
> 
> 
> > In the ineterest of learning Visual Basic I have created a PLL
> > Calulator application.  Please check it out and let me know of 
errors
> > or needed improvements.
> >
> > Richard
> >
> > http://f6.grp.yahoofs.com/v1/gLcsQY9uIEwnJWvckxURs-
> > 
ePoupA_QP15YeBrAAAfGA7g1fOPlytFjqLelO_9FJ90kP4nhn5gQJmIqoXGRpyWK5LI9mu
Show quoted textHide quoted text
> > /PLL_calculator.zip
> >
> >
> >
> >
> >
> > Yahoo! Groups Links
> >
> >
> >
> >
> >

Re: PLL not locking

2004-08-26 by Leighton Rowe

Just giving u an update guys.

(Custom Board with lpc2114 & 14.7456 MHz Xtal)

I was able to execute code on the custom board without using the PLL 
setup. Knowing that only the crystal's driving cclk, the system ran 
noticably slower than normal. 

However, whenever I add the code to enable the PLL, execution always 
get stuck at the part that waits for the PLL to lock.

ie...while(!(PLLSTAT & 0x0400));

If I continue the PLL setup without waiting the JTAG's gone 
completely, and I'll have to restart the board to ISP mode.

Now I tried the same code on the regular mcb2100 board (lpc2124 @ 
12MHz) ( M=4 P=2) and everything works fine as it should. The 
typical 12MHz ratio (M=5 P=2) that I use also works.

So, I can only conclude that the code's ok, but there's something 
wrong with the custom board's hardware setup, but I don't know 
exactly where to start. Anyone knows what else can cause the PLL not 
to lock?

Thanks in advance,
Leighton

--- In lpc2000@yahoogroups.com, "Leighton Rowe" <leightonsrowe@y...> 
wrote:
> Yep. PLLCFG's set to 0x23.
> 
> --- In lpc2000@yahoogroups.com, capiman@t... wrote:
> > Have you set PLLCFG = 0x23 (instead of 0x03 in your original 
> sample) ?
> > 
> > Regards,
> > 
> >         Martin
> > 
> > ----- Original Message ----- 
> > From: "Leighton Rowe" <leightonsrowe@y...>
> > To: <lpc2000@yahoogroups.com>
> > Sent: Wednesday, August 25, 2004 3:52 PM
> > Subject: [lpc2000] Re: PLL not locking
> > 
> > 
> > > All The IRQ/FIQ interrupts are disabled.
> > > 
> > > If I slowly step through with the debugger the PLLSTAT 
register 
> > > doesn't even change after the feed sequence
> > > 
> > > PLLSTAT shows 0
> > > 
> > > And if I just let it run, it will still be stuck in the wait 
for 
> > > lock loop...
> > > 
> > > PLLSTAT shows 0x0123 
> > > 
> > > ...so the PLL's enabled but not locked
> > > 
> > > My only guess is the board wasn't connected up as it should 
be. 
Show quoted textHide quoted text
> > > Since the code is executing, the crystal seems to be ok but 
> right 
> > > now, it's made not to carry a Reset button.
> > > 
> > > Leighton
> > > 
> > > --- In lpc2000@yahoogroups.com, "Uwe Arends" <Uwe_Arends@o...> 
> wrote:
> > >> Leighton,
> > >> 
> > >> > Ok then...forgot about the divider value. Well, I tried out 
> what 
> > > u said too. I expect it to work but apparently the PLL's still
> > >> not locking...Any ideas?
> > >> >
> > >> > > Your setting of PLLCFG would cause it to run at 
> 4*14.7456MHz * 
> > > 2 * 1 == 117.96MHz,
> > >> > > just outside the allowed range. Set P to 2 and you should 
> be 
> > > ok => PLLCFG = 0x23.
> > >> > >
> > >> <snip>
> > >> > > PLLFEED = 0xAA;
> > >> > > PLLFEED = 0x55;
> > >> <snip>
> > >> 
> > >> the only thing left I can think of is, that the feed sequence 
> > > doesn't do what it should.
> > >> Do you have interrupts enabled during the above?
> > >> 
> > >> -wue
> > > 
> > > 
> > > 
> > > 
> > > 
> > > Yahoo! Groups Links
> > > 
> > > 
> > > 
> > > 
> > >

Re: PLL not locking

2004-08-26 by Richard

It may be late in the game for code help but here is some working PLL 
code.  Make sure your PLL SFR defines are correct.

Richard

#define PLLCON     (*((volatile unsigned int *) 0xE01FC080))
#define PLLCFG     (*((volatile unsigned int *) 0xE01FC084))
#define PLLSTAT    (*((volatile unsigned int *) 0xE01FC088))
#define PLLFEED    (*((volatile unsigned int *) 0xE01FC08C))
#define PLOCK    (1<<10) 



 /* Initialize PLL */
      	        PLLCFG=0x23;
	        feed();
		PLLCON=0x1;
	        feed();
		while(!(PLLSTAT & PLOCK)){}
        	PLLCON=0x3;
	        feed(); 



 void feed()
	{
		PLLFEED=0xAA;
		PLLFEED=0x55;
	}





--- In lpc2000@yahoogroups.com, "Leighton Rowe" <leightonsrowe@y...> 
wrote:
> Just giving u an update guys.
> 
> (Custom Board with lpc2114 & 14.7456 MHz Xtal)
> 
> I was able to execute code on the custom board without using the 
PLL 
> setup. Knowing that only the crystal's driving cclk, the system ran 
> noticably slower than normal. 
> 
> However, whenever I add the code to enable the PLL, execution 
always 
> get stuck at the part that waits for the PLL to lock.
> 
> ie...while(!(PLLSTAT & 0x0400));
> 
> If I continue the PLL setup without waiting the JTAG's gone 
> completely, and I'll have to restart the board to ISP mode.
> 
> Now I tried the same code on the regular mcb2100 board (lpc2124 @ 
> 12MHz) ( M=4 P=2) and everything works fine as it should. The 
> typical 12MHz ratio (M=5 P=2) that I use also works.
> 
> So, I can only conclude that the code's ok, but there's something 
> wrong with the custom board's hardware setup, but I don't know 
> exactly where to start. Anyone knows what else can cause the PLL 
not 
> to lock?
> 
> Thanks in advance,
> Leighton
> 
> --- In lpc2000@yahoogroups.com, "Leighton Rowe" 
<leightonsrowe@y...> 
> wrote:
> > Yep. PLLCFG's set to 0x23.
> > 
> > --- In lpc2000@yahoogroups.com, capiman@t... wrote:
> > > Have you set PLLCFG = 0x23 (instead of 0x03 in your original 
> > sample) ?
> > > 
> > > Regards,
> > > 
> > >         Martin
> > > 
> > > ----- Original Message ----- 
> > > From: "Leighton Rowe" <leightonsrowe@y...>
> > > To: <lpc2000@yahoogroups.com>
> > > Sent: Wednesday, August 25, 2004 3:52 PM
> > > Subject: [lpc2000] Re: PLL not locking
> > > 
> > > 
> > > > All The IRQ/FIQ interrupts are disabled.
> > > > 
> > > > If I slowly step through with the debugger the PLLSTAT 
> register 
> > > > doesn't even change after the feed sequence
> > > > 
> > > > PLLSTAT shows 0
> > > > 
> > > > And if I just let it run, it will still be stuck in the wait 
> for 
> > > > lock loop...
> > > > 
> > > > PLLSTAT shows 0x0123 
> > > > 
> > > > ...so the PLL's enabled but not locked
> > > > 
> > > > My only guess is the board wasn't connected up as it should 
> be. 
> > > > Since the code is executing, the crystal seems to be ok but 
> > right 
> > > > now, it's made not to carry a Reset button.
> > > > 
> > > > Leighton
> > > > 
> > > > --- In lpc2000@yahoogroups.com, "Uwe Arends" 
<Uwe_Arends@o...> 
> > wrote:
> > > >> Leighton,
> > > >> 
> > > >> > Ok then...forgot about the divider value. Well, I tried 
out 
> > what 
> > > > u said too. I expect it to work but apparently the PLL's still
> > > >> not locking...Any ideas?
> > > >> >
> > > >> > > Your setting of PLLCFG would cause it to run at 
> > 4*14.7456MHz * 
> > > > 2 * 1 == 117.96MHz,
> > > >> > > just outside the allowed range. Set P to 2 and you 
should 
> > be 
> > > > ok => PLLCFG = 0x23.
> > > >> > >
> > > >> <snip>
> > > >> > > PLLFEED = 0xAA;
> > > >> > > PLLFEED = 0x55;
> > > >> <snip>
> > > >> 
> > > >> the only thing left I can think of is, that the feed 
sequence 
Show quoted textHide quoted text
> > > > doesn't do what it should.
> > > >> Do you have interrupts enabled during the above?
> > > >> 
> > > >> -wue
> > > > 
> > > > 
> > > > 
> > > > 
> > > > 
> > > > Yahoo! Groups Links
> > > > 
> > > > 
> > > > 
> > > > 
> > > >

Re: [lpc2000] Re: PLL not locking

2004-08-26 by Leighton Rowe

My registers are defined correctly.
But I notice that you used feed after every single PLL register write.
 
I was using the feeds a little bit differently
PLLCFG=0x23;
PLLCON=0x1;
....feed sequence
 
I got this from some example code by Keil. It worked fine with the mcb eval board but not with the lpc2114 I'm working on. 
 
I'll let u know how it goes tomorrow though...it's worth a try.
 
thanks,
Leighton

Richard <richas@...> wrote:
It may be late in the game for code help but here is some working PLL 
code.  Make sure your PLL SFR defines are correct.

Richard

#define PLLCON     (*((volatile unsigned int *) 0xE01FC080))
#define PLLCFG     (*((volatile unsigned int *) 0xE01FC084))
#define PLLSTAT    (*((volatile unsigned int *) 0xE01FC088))
#define PLLFEED    (*((volatile unsigned int *) 0xE01FC08C))
#define PLOCK    (1<<10) 



/* Initialize PLL */
                    PLLCFG=0x23;
              feed();
            PLLCON=0x1;
              feed();
            while(!(PLLSTAT & PLOCK)){}
              PLLCON=0x3;
              feed(); 



void feed()
      {
            PLLFEED=0xAA;
            PLLFEED=0x55;
      }





--- In lpc2000@yahoogroups.com, "Leighton Rowe" <leightonsrowe@y...> 
wrote:
> Just giving u an update guys.
> 
> (Custom Board with lpc2114 & 14.7456 MHz Xtal)
> 
> I was able to execute code on the custom board without using the 
PLL 
> setup. Knowing that only the crystal's driving cclk, the system ran 
> noticably slower than normal. 
> 
> However, whenever I add the code to enable the PLL, execution 
always 
> get stuck at the part that waits for the PLL to lock.
> 
> ie...while(!(PLLSTAT & 0x0400));
> 
> If I continue the PLL setup without waiting the JTAG's gone 
> completely, and I'll have to restart the board to ISP mode.
> 
> Now I tried the same code on the regular mcb2100 board (lpc2124 @ 
> 12MHz) ( M=4 P=2) and everything works fine as it should. The 
> typical 12MHz ratio (M=5 P=2) that I use also works.
> 
> So, I can only conclude that the code's ok, but there's something 
> wrong with the custom board's hardware setup, but I don't know 
> exactly where to start. Anyone knows what else can cause the PLL 
not 
> to lock?
> 
> Thanks in advance,
> Leighton
> 
> --- In lpc2000@yahoogroups.com, "Leighton Rowe" 
<leightonsrowe@y...> 
> wrote:
> > Yep. PLLCFG's set to 0x23.
> > 
> > --- In lpc2000@yahoogroups.com, capiman@t... wrote:
> > > Have you set PLLCFG = 0x23 (instead of 0x03 in your original 
> > sample) ?
> > > 
> > > Regards,
> > > 
> > >         Martin
> > > 
> > > ----- Original Message ----- 
> > > From: "Leighton Rowe" <leightonsrowe@y...>
> > > To: <lpc2000@yahoogroups.com>
> > > Sent: Wednesday, August 25, 2004 3:52 PM
> > > Subject: [lpc2000] Re: PLL not locking
> > > 
> > > 
> > > > All The IRQ/FIQ interrupts are disabled.
> > > > 
> > > > If I slowly step through with the debugger the PLLSTAT 
> register 
> > > > doesn't even change after the feed sequence
> > > > 
> > > > PLLSTAT shows 0
> > > > 
> > > > And if I just let it run, it will still be stuck in the wait 
> for 
> > > > lock loop...
> > > > 
> > > > PLLSTAT shows 0x0123 
> > > > 
> > > > ...so the PLL's enabled but not locked
> > > > 
> > > > My only guess is the board wasn't connected up as it should 
> be. 
> > > > Since the code is executing, the crystal seems to be ok but 
> > right 
> > > > now, it's made not to carry a Reset button.
> > > > 
> > > > Leighton
> > > > 
> > > > --- In lpc2000@yahoogroups.com, "Uwe Arends" 
<Uwe_Arends@o...> 
> > wrote:
> > > >> Leighton,
> > > >> 
> > > >> > Ok then...forgot about the divider value. Well, I tried 
out 
> > what 
> > > > u said too. I expect it to work but apparently the PLL's still
> > > >> not locking...Any ideas?
> > > >> >
> > > >> > > Your setting of PLLCFG would cause it to run at 
> > 4*14.7456MHz * 
> > > > 2 * 1 == 117.96MHz,
> > > >> > > just outside the allowed range. Set P to 2 and you 
should 
> > be 
> > > > ok => PLLCFG = 0x23.
> > > >> > >
> > > >> <snip>
> > > >> > > PLLFEED = 0xAA;
> > > >> > > PLLFEED = 0x55;
> > > >> <snip>
> > > >> 
> > > >> the only thing left I can think of is, that the feed 
sequence 
> > > > doesn't do what it should.
> > > >> Do you have interrupts enabled during the above?
> > > >> 
> > > >> -wue
> > > > 
> > > > 
> > > > 
> > > > 
> > > > 
> > > > Yahoo! Groups Links
> > > > 
> > > > 
> > > > 
> > > > 
> > > >


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[Non-text portions of this message have been removed]

Re: PLL not locking

2004-08-27 by philips_apps

> So, I can only conclude that the code's ok, but there's something 
> wrong with the custom board's hardware setup, but I don't know 
> exactly where to start. Anyone knows what else can cause the PLL 
not 
> to lock?

In the custom board all power supply pins may not be connected 
correctly. Check if pin 63 is connected to 1.8V and pin 58 to Vss.

Philips Apps

Re: PLL not locking

2004-08-27 by Leighton Rowe

Philips Apps, you have solved the problem. 

Pin 63 (V18a_pll) was showing 0.56V instead of the required 1.8V. 
Changes were made to the board and the PLL's locking like a dream.

Thanks a mil!
Leighton

--- In lpc2000@yahoogroups.com, "philips_apps" <philips_apps@y...> 
wrote:
> > So, I can only conclude that the code's ok, but there's 
something 
Show quoted textHide quoted text
> > wrong with the custom board's hardware setup, but I don't know 
> > exactly where to start. Anyone knows what else can cause the PLL 
> not 
> > to lock?
> 
> In the custom board all power supply pins may not be connected 
> correctly. Check if pin 63 is connected to 1.8V and pin 58 to Vss.
> 
> Philips Apps

PLL Calculator

2004-08-31 by Richard

New version in the files section, feedback please.

Thanks

Richard

Move to quarantaine

This moves the raw source file on disk only. The archive index is not changed automatically, so you still need to run a manual refresh afterward.