Lpc2000

It may be late in the game for code help but here is some working PLL 
code.  Make sure your PLL SFR defines are correct.

Richard

#define PLLCON     (*((volatile unsigned int *) 0xE01FC080))
#define PLLCFG     (*((volatile unsigned int *) 0xE01FC084))
#define PLLSTAT    (*((volatile unsigned int *) 0xE01FC088))
#define PLLFEED    (*((volatile unsigned int *) 0xE01FC08C))
#define PLOCK    (1<<10) 



 /* Initialize PLL */
      	        PLLCFG=0x23;
	        feed();
		PLLCON=0x1;
	        feed();
		while(!(PLLSTAT & PLOCK)){}
        	PLLCON=0x3;
	        feed(); 



 void feed()
	{
		PLLFEED=0xAA;
		PLLFEED=0x55;
	}





--- In lpc2000@yahoogroups.com, "Leighton Rowe" <leightonsrowe@y...> 
wrote:
> Just giving u an update guys.
> 
> (Custom Board with lpc2114 & 14.7456 MHz Xtal)
> 
> I was able to execute code on the custom board without using the 
PLL 
> setup. Knowing that only the crystal's driving cclk, the system ran 
> noticably slower than normal. 
> 
> However, whenever I add the code to enable the PLL, execution 
always 
> get stuck at the part that waits for the PLL to lock.
> 
> ie...while(!(PLLSTAT & 0x0400));
> 
> If I continue the PLL setup without waiting the JTAG's gone 
> completely, and I'll have to restart the board to ISP mode.
> 
> Now I tried the same code on the regular mcb2100 board (lpc2124 @ 
> 12MHz) ( M=4 P=2) and everything works fine as it should. The 
> typical 12MHz ratio (M=5 P=2) that I use also works.
> 
> So, I can only conclude that the code's ok, but there's something 
> wrong with the custom board's hardware setup, but I don't know 
> exactly where to start. Anyone knows what else can cause the PLL 
not 
> to lock?
> 
> Thanks in advance,
> Leighton
> 
> --- In lpc2000@yahoogroups.com, "Leighton Rowe" 
<leightonsrowe@y...> 
> wrote:
> > Yep. PLLCFG's set to 0x23.
> > 
> > --- In lpc2000@yahoogroups.com, capiman@t... wrote:
> > > Have you set PLLCFG = 0x23 (instead of 0x03 in your original 
> > sample) ?
> > > 
> > > Regards,
> > > 
> > >         Martin
> > > 
> > > ----- Original Message ----- 
> > > From: "Leighton Rowe" <leightonsrowe@y...>
> > > To: <lpc2000@yahoogroups.com>
> > > Sent: Wednesday, August 25, 2004 3:52 PM
> > > Subject: [lpc2000] Re: PLL not locking
> > > 
> > > 
> > > > All The IRQ/FIQ interrupts are disabled.
> > > > 
> > > > If I slowly step through with the debugger the PLLSTAT 
> register 
> > > > doesn't even change after the feed sequence
> > > > 
> > > > PLLSTAT shows 0
> > > > 
> > > > And if I just let it run, it will still be stuck in the wait 
> for 
> > > > lock loop...
> > > > 
> > > > PLLSTAT shows 0x0123 
> > > > 
> > > > ...so the PLL's enabled but not locked
> > > > 
> > > > My only guess is the board wasn't connected up as it should 
> be. 
> > > > Since the code is executing, the crystal seems to be ok but 
> > right 
> > > > now, it's made not to carry a Reset button.
> > > > 
> > > > Leighton
> > > > 
> > > > --- In lpc2000@yahoogroups.com, "Uwe Arends" 
<Uwe_Arends@o...> 
> > wrote:
> > > >> Leighton,
> > > >> 
> > > >> > Ok then...forgot about the divider value. Well, I tried 
out 
> > what 
> > > > u said too. I expect it to work but apparently the PLL's still
> > > >> not locking...Any ideas?
> > > >> >
> > > >> > > Your setting of PLLCFG would cause it to run at 
> > 4*14.7456MHz * 
> > > > 2 * 1 == 117.96MHz,
> > > >> > > just outside the allowed range. Set P to 2 and you 
should 
> > be 
> > > > ok => PLLCFG = 0x23.
> > > >> > >
> > > >> <snip>
> > > >> > > PLLFEED = 0xAA;
> > > >> > > PLLFEED = 0x55;
> > > >> <snip>
> > > >> 
> > > >> the only thing left I can think of is, that the feed 
sequence 
> > > > doesn't do what it should.
> > > >> Do you have interrupts enabled during the above?
> > > >> 
> > > >> -wue
> > > > 
> > > > 
> > > > 
> > > > 
> > > > 
> > > > Yahoo! Groups Links
> > > > 
> > > > 
> > > > 
> > > > 
> > > >