Lpc2000

If I remember correctly there are a few of things of note with JTAG and
the LPC2100 that we came across

1) the JTAG reset resets the TAP/ICE breaker registers. This makes
starting under debug control potentially problematic - i.e. there is a
window of opportunity after reset where the CPU can run before the
debugger can get the chip under debug control. We have many other ARM
chips/boards with odd reset behaviour so we put in a  JavaScript'able
reset capability into CrossWorks that can control the reset the debugger
does. For example the with ATMEL AT91 processors the watchdog can be
used to reset the CPU. 

2) the debug comms port requires synchronisation i.e. the status bit has
be tested to make debug comms work. I guess this is part of the spec but
things can go a lot quicker without testing the status bit - i.e. hoping
the ARM is faster than the host.

3) a lot of I/O pins are lost when you enable JTAG debugging.

I just did a quick test - CrossWorks can flash load an LPC2100 using a
wiggler at 13Kbytes per second? I know that we can flash load an
Evaluator7T at 18Kbytes per second. Can anyone comment on if we have hit
the limit on flash programming performance on the LPC2100?

Regards
Michael