Lpc2000

I'm considering the LPC221x for a data acquisition device, but I 
need multi-megabytes of SRAM (say, 16MB), and several parallel 
devices. I'll need multiple devices on the same memory channel, at 
different addresses.
Looking at the timing digrams for the address bus, I can't see how 
to reliably decode the address bus to generate extra CS signals: CS 
and OE can go low before OR after the address lines settle.

Any suggestions on how to qualify CS, OE or WE to allow multiple 
devices on the bus?