Lpc2000

I'm considering the LPC221x for a data acquisition device, but I 
need multi-megabytes of SRAM (say, 16MB), and several parallel 
devices. I'll need multiple devices on the same memory channel, at 
different addresses.
Looking at the timing digrams for the address bus, I can't see how 
to reliably decode the address bus to generate extra CS signals: CS 
and OE can go low before OR after the address lines settle.

Any suggestions on how to qualify CS, OE or WE to allow multiple 
devices on the bus?

You can use XCLK to delay CS.  That will give the address bus time
to stablize.

Regards
-Bill Knight
http://www.theARMPatch.com


On Mon, 01 Nov 2004 23:18:53 -0000, Damon Kelly wrote:



I'm considering the LPC221x for a data acquisition device, but I 
need multi-megabytes of SRAM (say, 16MB), and several parallel 
devices. I'll need multiple devices on the same memory channel, at 
different addresses.
Looking at the timing digrams for the address bus, I can't see how 
to reliably decode the address bus to generate extra CS signals: CS 
and OE can go low before OR after the address lines settle.

Any suggestions on how to qualify CS, OE or WE to allow multiple 
devices on the bus?

Not exactly sure what you mean there...

I just found a Sharp App Note about this very topic. They suggest a 
flip-flop clocked by XCLK, and Set by nCS, to delay nOE.

I figure clocking nOE on the -ve going edge of XCLK will give half a 
cycle delay.

nWE doesn't have the same problem -- it seems to always fall within 
nCS and Address Valid.

Damon

--- In lpc2000@yahoogroups.com, "Bill Knight" <BillK@t...> wrote:
> You can use XCLK to delay CS.  That will give the address bus time
> to stablize.
> 
> Regards
> -Bill Knight
> http://www.theARMPatch.com
> 
> 
> On Mon, 01 Nov 2004 23:18:53 -0000, Damon Kelly wrote:
> 
> 
> 
> I'm considering the LPC221x for a data acquisition device, but I 
> need multi-megabytes of SRAM (say, 16MB), and several parallel 
> devices. I'll need multiple devices on the same memory channel, at 
> different addresses.
> Looking at the timing digrams for the address bus, I can't see how 
> to reliably decode the address bus to generate extra CS signals: 
CS 

> and OE can go low before OR after the address lines settle.
> 
> Any suggestions on how to qualify CS, OE or WE to allow multiple 
> devices on the bus?

Hi,

The past is coming to life again....

I just found the message below that was sent almost a year ago to the 
LPC2000 forum and I'm just attempting to do the same thing as the 
original poster.

Having looked at this, I have come to the same conclusion as Bill - 
use XCLK to produce a new derived CS dependent on the address. The 
question I have is 'how does this affect the required access time for 
the device'. The timing parameters given in the LPC2294 data sheet 
don't seem complete enough to make this determination. If I knew the 
actual point in the cycle when the data had to be valid then it would 
be easy, but that isn't specified.

Anybody have any ideas on this?

Andy..

--- In lpc2000@yahoogroups.com, "Bill Knight" <BillK@t...> wrote:

>
> You can use XCLK to delay CS.  That will give the address bus time
> to stablize.
> 
> Regards
> -Bill Knight
> http://www.theARMPatch.com
> 
> 
> On Mon, 01 Nov 2004 23:18:53 -0000, Damon Kelly wrote:
> 
> 
> 
> I'm considering the LPC221x for a data acquisition device, but I 
> need multi-megabytes of SRAM (say, 16MB), and several parallel 
> devices. I'll need multiple devices on the same memory channel, at 
> different addresses.
> Looking at the timing digrams for the address bus, I can't see how 
> to reliably decode the address bus to generate extra CS signals: CS 
> and OE can go low before OR after the address lines settle.
> 
> Any suggestions on how to qualify CS, OE or WE to allow multiple 
> devices on the bus?
>