Lpc2000

At 07:00 PM 11/18/04 +0000, you wrote:
> > Do you know (and can you tell) if the packet is truncated or maybe
>just
> > missing characters from its body?  If it always just characters at
>the end
> > I'm less optimistic about the race condition.
>
>Well after double checking & changing my code to the single IIR read
>concept, things remained the same. The affected packet I receive
>always get's somewhat truncated in the middle, with the last bytes
>showing up a few bytes earlier than expected.

Well that fits with the speculation of an IIR race condition.  Doesn't 
prove it but it does fit.  You may have duplicated what I've been seeing.


>I however notice LSR interrupt occuring at the point where the
>problem occurs but I don't see any signs of any LSR errors.

Hmmm... Doesn't make much sense to me either.  Maybe instead of a simple 
race the source is being miss-classified?  My own test would not have seen 
a difference between that and the interrupt simply dissappearing.


>Just a crazy question though...can the UART ISR interrupt itself?
>(eg. while processing a THRE an RDA interrupt comes in)

At the very least that would require that you re-enable the associated 
interrupt (IRQ or FIQ) and if vectored through the VIC you would also have 
to acknowledge the vectored interrupt with the appropriate write to the VIC 
first as well.   If you've done that, try it again w/o re-enabling the 
interrupts.


>Should I enable the FIFOs (write 1 to U0FCR) before running the
>interrupts? I seem to be getting by without this up until this point.

I don't see why that would eliminate the problem.  Worse it might hide it 
so that it showed up later under less benign conditions.

Curiouser and curiouser
Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III