Lpc2000

It seems to me that given the problem with the UART interrupt 
register, it is more likely than not that the same problem exists 
with other registers.  Rather than "one race condition is an 
oversight," I would assume similar circuit design would be used in 
all parts of the chip.

In any event, this is something which should be very easy for 
Philips' circuit designers to answer.

As engineers, we can all appreciate that bugs sometimes get through.  
It's the lack of information, once the bug is discovered, that's 
frustrating.


--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> 
wrote:
> 
> Well, one race condition is an oversight.  Two make me wonder if it 
was 
> something they didn't check for properly.  And since both the SPI 
and timer 
> have documented race conditions (and given the apparent long lead 
time 
> between the discovery of an issue and letting us know about it) ....
> 
> 
> >In fact, there are a number of other registers which also get 
written
> >to by both the core and peripheral hardware.  Has Philips analyzed
> >which of these are subject to the same problem with simultaneoues
> >access?
> >
> >Philips: How about letting us know what's going on!
> 
> Very good question.  Having errata come out in dribs and drabs is 
very 
> frustrating.
>