Lpc2000

--- In lpc2000@yahoogroups.com, "peterburdine" <lordofdawn@h...>
wrote:
> 
> Has anyone had experience with their UART fifos being randomly
> disabled?  For some reason, my UART0 fifo is being diabled seemingly
> randomly.  The application itself is not that complex, it receives
a 2
> byte command and sends back 10 bytes of status.  Somehow, the fifos
> get disabled, then a CTI interrupt occurs that I cannot get rid of. 
> In the manual it says to clear CTI I need to read RSR.  I don't see
an
> RSR register, but I would assume that they meant RBR.
RSR stands for Receiver Shift Register. It's program invisible and
connected directly to RBR (See UART architecture block diagram). So
reading should update RSR status.
> 
> Any suggestions?
> 
> Thanks,
> Peter
Hi, Peter

I am interesting which "UART interrupt handling" (U?IIR[3:0]) mode you
use?