Lpc2000

--- In lpc2000@yahoogroups.com, "peterburdine" <lordofdawn@h...> 
wrote:
> 
> --- In lpc2000@yahoogroups.com, "emerg_reanimator"
> <emerg_reanimator@y...> wrote:
> > 
> > --- In lpc2000@yahoogroups.com, "peterburdine" <lordofdawn@h...>
> > wrote:
> > > 
> > > Has anyone had experience with their UART fifos being randomly
> > > disabled?  For some reason, my UART0 fifo is being diabled 
seemingly
> > > randomly.  The application itself is not that complex, it 
receives
> > a 2
> > > byte command and sends back 10 bytes of status.  Somehow, the 
fifos
> > > get disabled, then a CTI interrupt occurs that I cannot get 
rid of. 
> > > In the manual it says to clear CTI I need to read RSR.  I 
don't see
> > an
> > > RSR register, but I would assume that they meant RBR.
> > RSR stands for Receiver Shift Register. It's program invisible 
and
> > connected directly to RBR (See UART architecture block diagram). 
So
> > reading should update RSR status.
> > > 
> > > Any suggestions?
> > > 
> > > Thanks,
> > > Peter
> > Hi, Peter
> > 
> > I am interesting which "UART interrupt handling" (U?IIR[3:0]) 
mode you
> > use?
> 
> 
> I am using RBR and THRE.  I probably should have also noted that 
this
> is a motor control board so the data receveived on UART0 is 
commands
> to change the PWM (2&5).

Peter,

You are correct that you "read the RSR" by reading a character from 
the RBR.  You must, however handle CTI interrupts.  These can be 
handled using the same code as the RDA handler.  If the FIFO has a 
few characters in it for the length of the timeout period, the CTI 
interrupt will fire and, if the characters are not read, CTI will 
not clear and the FIFOs will cease to operate.  Sounds like this 
might be the problem.

Good luck,
Randy Ott