Lpc2000

> In the example the VPB divider was 4, I now tried with 1 and I got a
> Freq of 3,50 MHz, that are 17 clock cycles for 1 period.
> It should be only 16 (like discribed in the link in FAQ) ... at the
> moment I don't know the cause of the extra clock.

Could it be an extra wait state for the CPU to be granted access to the VPB
bus ???

-- Kris