Lpc2000

I just looked at the cycle timing specs of the ARM7TDMI-S and I must
say.. I don't understand it.
I made the following test:
- Programm is running in flash
- MAM is at max speed
- PLL is set to M = 5 and P = 2 @ 12 MHz Foc -> 60 MHz cclk
- Pogramm is 100% THUMB, assembler coded
- r2 holds IO1SET, r0 holds IO1CLR, r1 holds the bit position
- I am scoping the the following loop:

loop:
   str r1, [r0]
   str r1, [r2]
   b loop

The scope shows a frequency of about 1,666 MHz at the output pin. With
some testing, eg doubling one of the str, i figgured out that the b is
nearly done in 1 cclk cycle. But the 1,666 MHz will mean that one str
takes about 18 cclk cycles( also tested with PLL off, same result the
Freq is exactly 1/5).
Now there are 2 things that I don't understand:
1. 18 cycles lookes very long to me. Can that be?
1. How can I calculate the exact value of the instructions?

regards

Thomas

At 10:56 PM 11/30/04 +0000, you wrote:


>I just looked at the cycle timing specs of the ARM7TDMI-S and I must
>say.. I don't understand it.
>I made the following test:
>- Programm is running in flash
>- MAM is at max speed
>- PLL is set to M = 5 and P = 2 @ 12 MHz Foc -> 60 MHz cclk
>- Pogramm is 100% THUMB, assembler coded
>- r2 holds IO1SET, r0 holds IO1CLR, r1 holds the bit position
>- I am scoping the the following loop:

Just added to the earlier mentioned FAQ.  This is the question I most 
expected to be asked.

http://www.open-research.org.uk/ARMuC/index.cgi?LPC2100Tips

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

--- In lpc2000@yahoogroups.com, "digtalfreak" <digitalfreak@n...> 
wrote:
> 
> I just looked at the cycle timing specs of the ARM7TDMI-S and I must
> say.. I don't understand it.
> I made the following test:
> - Programm is running in flash
> - MAM is at max speed
> - PLL is set to M = 5 and P = 2 @ 12 MHz Foc -> 60 MHz cclk
> - Pogramm is 100% THUMB, assembler coded
> - r2 holds IO1SET, r0 holds IO1CLR, r1 holds the bit position
> - I am scoping the the following loop:
> 
> loop:
>    str r1, [r0]
>    str r1, [r2]
>    b loop
> 
> The scope shows a frequency of about 1,666 MHz at the output pin. 
With
> some testing, eg doubling one of the str, i figgured out that the b 
is
> nearly done in 1 cclk cycle. But the 1,666 MHz will mean that one 
str
> takes about 18 cclk cycles( also tested with PLL off, same result 
the
> Freq is exactly 1/5).
> Now there are 2 things that I don't understand:
> 1. 18 cycles lookes very long to me. Can that be?
> 1. How can I calculate the exact value of the instructions?

Have you changed the VPB divider from the default 4 to 1?

Karl Olsen

Thanks, that link helped very much. I also thought about the
pipelining but I din't understand how to get from cycles to needed clocks.

I need to know the timing calculation very exactly. At the example
with the str the cycles, like described at the link, are:

Fetch(1clk)+Decode(1clk)+N-Cycle(2clk)+N-Cycle(4clk)

First N-Cycle is clear to me, its a normal N-Cycle on the AHB.
But the second N-Cycle, targeting a register on VPB, is very unclear
to me. I can't find any documentation of the AHB-VPB Bridge and how it
influences the length of the N-Cycle but I need that for my documentation.

regards

Thomas

--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> wrote:

> 
> Just added to the earlier mentioned FAQ.  This is the question I most 
> expected to be asked.
> 
> http://www.open-research.org.uk/ARMuC/index.cgi?LPC2100Tips
> 
> Robert
> 
> " 'Freedom' has no meaning of itself.  There are always restrictions,
> be they legal, genetic, or physical.  If you don't believe me, try to
> chew a radio signal. "
> 
>                          Kelvin Throop, III

In the example the VPB divider was 4, I now tried with 1 and I got a
Freq of 3,50 MHz, that are 17 clock cycles for 1 period.
It should be only 16 (like discribed in the link in FAQ) ... at the
moment I don't know the cause of the extra clock.

--- In lpc2000@yahoogroups.com, "Karl Olsen" <kro@p...> wrote:

> Have you changed the VPB divider from the default 4 to 1?
> 
> Karl Olsen

> In the example the VPB divider was 4, I now tried with 1 and I got a
> Freq of 3,50 MHz, that are 17 clock cycles for 1 period.
> It should be only 16 (like discribed in the link in FAQ) ... at the
> moment I don't know the cause of the extra clock.

Could it be an extra wait state for the CPU to be granted access to the VPB
bus ???

-- Kris

> I need to know the timing calculation very exactly. At the example
> with the str the cycles, like described at the link, are:

Just in case this is what you're doing: *In general* it is wise to avoid
using software timing on cores like ARM. Although it's quite
deterministic on the uncached variants, your code will break
spectacularly and unfixably if you ever migrate to a higher-end part.

-- 
Lewin A.R.W. Edwards
Consulting - http://www.zws.com/
Personal   - http://www.larwe.com/
Check out my books on embedded engineering!
<http://www.amazon.com/exec/obidos/ASIN/0750676094/zws-20/>
<http://www.amazon.com/exec/obidos/ASIN/0750677783/zws-20/>

No I don't wan't to use that for timing the software. I only need that
for documentation.
Today I was seraching very intensive for some infos about the timing.
I know think to understand it a bit better, but not all.

So what I found out is that the cycle timing is the base, but the
lenght for example of a N-Cycle, is much dempending on the hardware
after the AHB. A str takes 2 N-Cycles, but you can't say how many
cclk-cycles a N-Cycle will last. Because the N-Cycle can be made
longer by the addressed hardware after the AHB.
Looking on the Block diagramm of the LPC2129 shows that there are 3-4
different read/write possibilities.
1. read/(write) on FLASH
2. read/write on RAM
3. read/write on adresses mapped directly to the AHB
4. read/write on adresses mapped to the VPB

All operations will have the same count of N-Cycles, but they all
will/can take different time.
So the final question I have is: Can someone tell me the exact
calculation of the N-cycle-length in the different cases?
But maybe this question can only be answered by a designer of the LPC...

--- In lpc2000@yahoogroups.com, "Lewin A.R.W. Edwards" <larwe@l...> wrote:

> > I need to know the timing calculation very exactly. At the example
> > with the str the cycles, like described at the link, are:
> 
> Just in case this is what you're doing: *In general* it is wise to avoid
> using software timing on cores like ARM. Although it's quite
> deterministic on the uncached variants, your code will break
> spectacularly and unfixably if you ever migrate to a higher-end part.
> 
> -- 
> Lewin A.R.W. Edwards
> Consulting - http://www.zws.com/
> Personal   - http://www.larwe.com/
> Check out my books on embedded engineering!
> <http://www.amazon.com/exec/obidos/ASIN/0750676094/zws-20/>
> <http://www.amazon.com/exec/obidos/ASIN/0750677783/zws-20/>