Lpc2000

No I don't wan't to use that for timing the software. I only need that
for documentation.
Today I was seraching very intensive for some infos about the timing.
I know think to understand it a bit better, but not all.

So what I found out is that the cycle timing is the base, but the
lenght for example of a N-Cycle, is much dempending on the hardware
after the AHB. A str takes 2 N-Cycles, but you can't say how many
cclk-cycles a N-Cycle will last. Because the N-Cycle can be made
longer by the addressed hardware after the AHB.
Looking on the Block diagramm of the LPC2129 shows that there are 3-4
different read/write possibilities.
1. read/(write) on FLASH
2. read/write on RAM
3. read/write on adresses mapped directly to the AHB
4. read/write on adresses mapped to the VPB

All operations will have the same count of N-Cycles, but they all
will/can take different time.
So the final question I have is: Can someone tell me the exact
calculation of the N-cycle-length in the different cases?
But maybe this question can only be answered by a designer of the LPC...

--- In lpc2000@yahoogroups.com, "Lewin A.R.W. Edwards" <larwe@l...> wrote:
> > I need to know the timing calculation very exactly. At the example
> > with the str the cycles, like described at the link, are:
> 
> Just in case this is what you're doing: *In general* it is wise to avoid
> using software timing on cores like ARM. Although it's quite
> deterministic on the uncached variants, your code will break
> spectacularly and unfixably if you ever migrate to a higher-end part.
> 
> -- 
> Lewin A.R.W. Edwards
> Consulting - http://www.zws.com/
> Personal   - http://www.larwe.com/
> Check out my books on embedded engineering!
> <http://www.amazon.com/exec/obidos/ASIN/0750676094/zws-20/>
> <http://www.amazon.com/exec/obidos/ASIN/0750677783/zws-20/>