Lpc2000

--- In lpc2000@yahoogroups.com, Owen Mooney <ojm@s...> wrote:
> Thanks for the replies on this. I'm a software engineer learning
hardware...
> 
> But the suggestion:
> 
> "On the chip side, fan out all the traces at least 1 cm away from the 
> chip, terminating at vias...consider the vias to be the start of your 
> routing, not the pins on the chip. "
> 
> Would actually make some of the vias off the board!! - 
> 
> I will certainly add some capacitors - I should be able to get at
least 3 under the chip.

< long post > 

I'm not trying to put anyone down, but software people normally need
to learn a lot before attempting to do a hardware design.  Power
decoupling is one of the areas where there are a lot of misconceptions
and the board can be very unforgiving.  Most of the newer ARM chips
use a separate voltage for the core and the IO drivers.  This is good
for decoupling because they have different problems.  The IOs need to
be well decoupled because driving external lines can require large
transient currents during switching.  If the decoupling between Vdd
pins and Vss pins is not up to snuff, you will see this current
produce a large voltage on the ground and power pins.  This can cause
errors because the chip sees incorrect voltages between the grounds
and the signals.  It can even cause the clock to double strobe.  

The core supply is also important to decouple because of the higher
clock rates and edge rates inside the chip.  If you get voltage spikes
on the Vcore rail, you can see transient errors in calculations and
execution.  This will be *VERY* hard to debug.  

So do not skimp on the decoupling.  You may get away with it, or you
may end up with a flakey board that is nearly impossible to debug.  

Now for the correct (or maybe ideal) decoupling method...  Use one 0.1
uF ceramic cap per Vdd pin.  Route the other side of the cap to the
nearest Vss pin with as short a loop area as possible.  The area of
the loop is what is important since the goal is to minimize inductance
and that depends on the area of the loop.  Don't underestimate the
importance of this since the edge rates are the culprit here, not the
clock speed and edge rates can be very high (>500 MHz easily) Each
voltage rail should also have at least one healthy tantalum or
electrolytic cap, 10 uF or larger.  This will help with droop
(frequencies lower than the clock speed).  I made a board once where I
used 10 uF and had an analog circuit that was very sensitive to power
noise.  The DSP was in a 300 Hz loop passing blocks of data to and
from the codec.  Guess what, I got a low level 300 Hz hum in the
audio.  The real problem was the audio component that had exactly 0 dB
of PSRR, but a larger cap would have masked the problem adequately.  

Hope I didn't over load anyone with a long post.