Lpc2000

I hope this question is not too ignorant!

Is it necessary to link to all the VSS and VDD lines in the chip?

I'm working on a tight 2 layer layout.

Why are there so many?

Owen Mooney

At 09:59 AM 2/9/05 +1300, Owen Mooney wrote:
>I hope this question is not too ignorant!
>Is it necessary to link to all the VSS and VDD lines in the chip?

I haven't seen any indication otherwise.

>I'm working on a tight 2 layer layout.
>Why are there so many?


So many?  I only counted 4 (well 3 1/2) sets (one per side for the 2106).

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III

----- Original Message ----- 

From: "Owen Mooney" <ojm@...>
To: <lpc2000@yahoogroups.com>
Sent: Tuesday, February 08, 2005 8:59 PM
Subject: [lpc2000] VSS and VDD lines


>
> I hope this question is not too ignorant!
>
> Is it necessary to link to all the VSS and VDD lines in the chip?
>
> I'm working on a tight 2 layer layout.
>
> Why are there so many?

I wouldn't just tie them together, I'd decouple each Vdd pin with its own 
capacitor. That's why they are brought out to separate pins.

Leon 



-- 
No virus found in this outgoing message.
Checked by AVG Anti-Virus.
Version: 7.0.300 / Virus Database: 265.8.6 - Release Date: 07/02/2005

Owen,

if anything the LPC2000 devices do not have enough VDD/VSS pairs. If
you do not connect them all the chip MIGHT still run but usually the
pairs are responsible to provide power to logical blocks close to the
pins. Internally power is usually connected but you might loose some
voltage along the internal power traces.  If you do so, you reduce the
possible performance of the chip. 
As a result you could see random effects of some stuff not working or
temperature dependencies, almost impossible to find with debugging.
To avoid this trouble either for you and / or your customers, you
really want to connect all VDD/VSS pairs. For a clean power you should
also follow Leon's proposal to decouple each pair.

hth, Bob

--- In lpc2000@yahoogroups.com, "Leon Heller" <leon.heller@d...> wrote:
> ----- Original Message ----- 
> From: "Owen Mooney" <ojm@s...>
> To: <lpc2000@yahoogroups.com>
> Sent: Tuesday, February 08, 2005 8:59 PM
> Subject: [lpc2000] VSS and VDD lines
> 
> 
> >
> > I hope this question is not too ignorant!
> >
> > Is it necessary to link to all the VSS and VDD lines in the chip?
> >
> > I'm working on a tight 2 layer layout.
> >
> > Why are there so many?
> 
> I wouldn't just tie them together, I'd decouple each Vdd pin with
its own 

> capacitor. That's why they are brought out to separate pins.
> 
> Leon 
> 
> 
> 
> -- 
> No virus found in this outgoing message.
> Checked by AVG Anti-Virus.
> Version: 7.0.300 / Virus Database: 265.8.6 - Release Date: 07/02/2005

A quad package on a 2 layer board is one of the more annoying layout 
problems, except just be glad you're not dealing with a BGA.

On the chip side, fan out all the traces at least 1 cm away from the 
chip, terminating at vias...consider the vias to be the start of your 
routing, not the pins on the chip.  Don't bring out any logic vias 
under the chip, this leaves you maneuvering room.  Run wide VSS and 
VDD traces on the non-chip side of the board to a 10 to 50 ufd 
Tantalum located right under the chip.  From the leads of the 
Tantalum, spider out individual traces to each of the VDD/VSS pairs, 
with at least a 100nf capacitor located as near as possible to each 
pair. This individual decoupling of each VDD/VSS pair is essential.  
Remember your reputation rides on your product, take whatever time 
needed to do it right.

A major point is to try to mount all the discretes on the side 
opposite the chips, this makes your topside fanouts and routing a lot 
easier to deal with, and the board fab will love you much more if 
you're going that route.

Bill T.
http://www.kupercontrols.com

If you're struggling for space, why not use 0603 or smaller caps? 

---------------------------------------------------------------------------------

Owen,

if anything the LPC2000 devices do not have enough VDD/VSS pairs. If
you do not connect them all the chip MIGHT still run but usually the
pairs are responsible to provide power to logical blocks close to the
pins. Internally power is usually connected but you might loose some
voltage along the internal power traces.  If you do so, you reduce the
possible performance of the chip. 
As a result you could see random effects of some stuff not working or
temperature dependencies, almost impossible to find with debugging.
To avoid this trouble either for you and / or your customers, you
really want to connect all VDD/VSS pairs. For a clean power you should
also follow Leon's proposal to decouple each pair.

hth, Bob

--- In lpc2000@yahoogroups.com, "Leon Heller" <leon.heller@d...> wrote:
> ----- Original Message ----- 
> From: "Owen Mooney" <ojm@s...>
> To: <lpc2000@yahoogroups.com>
> Sent: Tuesday, February 08, 2005 8:59 PM
> Subject: [lpc2000] VSS and VDD lines
> 
> 
> >
> > I hope this question is not too ignorant!
> >
> > Is it necessary to link to all the VSS and VDD lines in the chip?
> >
> > I'm working on a tight 2 layer layout.
> >
> > Why are there so many?
> 
> I wouldn't just tie them together, I'd decouple each Vdd pin with
its own 
> capacitor. That's why they are brought out to separate pins.
> 
> Leon 
> 
> 
> 
> -- 
> No virus found in this outgoing message.
> Checked by AVG Anti-Virus.
> Version: 7.0.300 / Virus Database: 265.8.6 - Release Date: 07/02/2005





 
Yahoo! Groups Links

Thanks for the replies on this. I'm a software engineer learning hardware...

But the suggestion:

"On the chip side, fan out all the traces at least 1 cm away from the 
chip, terminating at vias...consider the vias to be the start of your 
routing, not the pins on the chip. "

Would actually make some of the vias off the board!! - 

I will certainly add some capacitors - I should be able to get at least 3 under the chip.

Owen

--- In lpc2000@yahoogroups.com, Owen Mooney <ojm@s...> wrote:
> Thanks for the replies on this. I'm a software engineer learning
hardware...
> 
> But the suggestion:
> 
> "On the chip side, fan out all the traces at least 1 cm away from the 
> chip, terminating at vias...consider the vias to be the start of your 
> routing, not the pins on the chip. "
> 
> Would actually make some of the vias off the board!! - 
> 
> I will certainly add some capacitors - I should be able to get at
least 3 under the chip.

< long post > 

I'm not trying to put anyone down, but software people normally need
to learn a lot before attempting to do a hardware design.  Power
decoupling is one of the areas where there are a lot of misconceptions
and the board can be very unforgiving.  Most of the newer ARM chips
use a separate voltage for the core and the IO drivers.  This is good
for decoupling because they have different problems.  The IOs need to
be well decoupled because driving external lines can require large
transient currents during switching.  If the decoupling between Vdd
pins and Vss pins is not up to snuff, you will see this current
produce a large voltage on the ground and power pins.  This can cause
errors because the chip sees incorrect voltages between the grounds
and the signals.  It can even cause the clock to double strobe.  

The core supply is also important to decouple because of the higher
clock rates and edge rates inside the chip.  If you get voltage spikes
on the Vcore rail, you can see transient errors in calculations and
execution.  This will be *VERY* hard to debug.  

So do not skimp on the decoupling.  You may get away with it, or you
may end up with a flakey board that is nearly impossible to debug.  

Now for the correct (or maybe ideal) decoupling method...  Use one 0.1
uF ceramic cap per Vdd pin.  Route the other side of the cap to the
nearest Vss pin with as short a loop area as possible.  The area of
the loop is what is important since the goal is to minimize inductance
and that depends on the area of the loop.  Don't underestimate the
importance of this since the edge rates are the culprit here, not the
clock speed and edge rates can be very high (>500 MHz easily) Each
voltage rail should also have at least one healthy tantalum or
electrolytic cap, 10 uF or larger.  This will help with droop
(frequencies lower than the clock speed).  I made a board once where I
used 10 uF and had an analog circuit that was very sensitive to power
noise.  The DSP was in a 300 Hz loop passing blocks of data to and
from the codec.  Guess what, I got a low level 300 Hz hum in the
audio.  The real problem was the audio component that had exactly 0 dB
of PSRR, but a larger cap would have masked the problem adequately.  

Hope I didn't over load anyone with a long post.

Is this a serious design or just to play with the chip ?
If it is for playing than it is cheaper to buy an eval board (see 
Olimex)
If it is serious, with 2 layer, you have very little chance to go 
through EMC aprovals. Check what is the difference in price between 2 
and 4 layer pcb and compare it to the value of your time.
(see other email for the rules of decoupling)
good luck
Jan


--- In lpc2000@yahoogroups.com, Owen Mooney <ojm@s...> wrote:

> I hope this question is not too ignorant!
> 
> Is it necessary to link to all the VSS and VDD lines in the chip?
> 
> I'm working on a tight 2 layer layout.
> 
> Why are there so many?
> 
> Owen Mooney

Jan,

In our case, using a LPC2214 and a two layer board. We had 
no problems with compliance testing.  In fact our very first 
board using this part, passed with quite a wide margin.

In our experience, it's rarely the cpu that causes problems
with EMC, but all the other stuff that's on the board, or 
what the board connects to.

Do to the volumes we produce, we always start with two layers, 
and all parts on one side.  We only go to more layers if we 
have to...

From the manufacturing costs, two layer and all parts on one 
side is the cheapest board to build.

Tim Larson


--- In lpc2000@yahoogroups.com, "Jan Szymanski" <janek@b...> wrote:
> 
> Is this a serious design or just to play with the chip ?
> If it is for playing than it is cheaper to buy an eval board (see 
> Olimex)
> If it is serious, with 2 layer, you have very little chance to go 
> through EMC aprovals. Check what is the difference in price 
between 2 

> and 4 layer pcb and compare it to the value of your time.
> (see other email for the rules of decoupling)
> good luck
> Jan
> 
> 
> --- In lpc2000@yahoogroups.com, Owen Mooney <ojm@s...> wrote:
> > I hope this question is not too ignorant!
> > 
> > Is it necessary to link to all the VSS and VDD lines in the chip?
> > 
> > I'm working on a tight 2 layer layout.
> > 
> > Why are there so many?
> > 
> > Owen Mooney

Tim,

my experience with CPUs as major cause for trouble in EMC testing
seems a little different. Fortunately the LPC2000 devices have a slew
rate of 10 ns, this makes the bus rather non-critical for EMC. Many
devices drive the bus with "all they have got" in the drivers and this
generates massive EMC problems. 

Cheers, Bob

--- In lpc2000@yahoogroups.com, "tlarson_greatnotions" <tlarson@g...>
wrote:

> 
> Jan,
> 
> In our case, using a LPC2214 and a two layer board. We had 
> no problems with compliance testing.  In fact our very first 
> board using this part, passed with quite a wide margin.
> 
> In our experience, it's rarely the cpu that causes problems
> with EMC, but all the other stuff that's on the board, or 
> what the board connects to.
> 
> Do to the volumes we produce, we always start with two layers, 
> and all parts on one side.  We only go to more layers if we 
> have to...
> 
> From the manufacturing costs, two layer and all parts on one 
> side is the cheapest board to build.
> 
> Tim Larson
> 
> 
> --- In lpc2000@yahoogroups.com, "Jan Szymanski" <janek@b...> wrote:
> > 
> > Is this a serious design or just to play with the chip ?
> > If it is for playing than it is cheaper to buy an eval board (see 
> > Olimex)
> > If it is serious, with 2 layer, you have very little chance to go 
> > through EMC aprovals. Check what is the difference in price 
> between 2 
> > and 4 layer pcb and compare it to the value of your time.
> > (see other email for the rules of decoupling)
> > good luck
> > Jan
> > 
> > 
> > --- In lpc2000@yahoogroups.com, Owen Mooney <ojm@s...> wrote:
> > > I hope this question is not too ignorant!
> > > 
> > > Is it necessary to link to all the VSS and VDD lines in the chip?
> > > 
> > > I'm working on a tight 2 layer layout.
> > > 
> > > Why are there so many?
> > > 
> > > Owen Mooney