Lpc2000

Tim,

my experience with CPUs as major cause for trouble in EMC testing
seems a little different. Fortunately the LPC2000 devices have a slew
rate of 10 ns, this makes the bus rather non-critical for EMC. Many
devices drive the bus with "all they have got" in the drivers and this
generates massive EMC problems. 

Cheers, Bob

--- In lpc2000@yahoogroups.com, "tlarson_greatnotions" <tlarson@g...>
wrote:
> 
> Jan,
> 
> In our case, using a LPC2214 and a two layer board. We had 
> no problems with compliance testing.  In fact our very first 
> board using this part, passed with quite a wide margin.
> 
> In our experience, it's rarely the cpu that causes problems
> with EMC, but all the other stuff that's on the board, or 
> what the board connects to.
> 
> Do to the volumes we produce, we always start with two layers, 
> and all parts on one side.  We only go to more layers if we 
> have to...
> 
> From the manufacturing costs, two layer and all parts on one 
> side is the cheapest board to build.
> 
> Tim Larson
> 
> 
> --- In lpc2000@yahoogroups.com, "Jan Szymanski" <janek@b...> wrote:
> > 
> > Is this a serious design or just to play with the chip ?
> > If it is for playing than it is cheaper to buy an eval board (see 
> > Olimex)
> > If it is serious, with 2 layer, you have very little chance to go 
> > through EMC aprovals. Check what is the difference in price 
> between 2 
> > and 4 layer pcb and compare it to the value of your time.
> > (see other email for the rules of decoupling)
> > good luck
> > Jan
> > 
> > 
> > --- In lpc2000@yahoogroups.com, Owen Mooney <ojm@s...> wrote:
> > > I hope this question is not too ignorant!
> > > 
> > > Is it necessary to link to all the VSS and VDD lines in the chip?
> > > 
> > > I'm working on a tight 2 layer layout.
> > > 
> > > Why are there so many?
> > > 
> > > Owen Mooney