Lpc2000

Hi Wayne,

> RESET is asserted for 200 ms after the power supply voltages are
> stable, then released.  The PCB is 12 layer, controlled impedance
> design with a great deal of bypassing and filtering.

If RESET is really held low for that time, then the slew rate shouldn't
matter
AFAIK. Are you sure nRST and nTRST are sound ?
Boot pin ? Held properly while RESET is de-asserted ?
This might result in erratic entry into bootloader etc.

B rgds
Kris