Lpc2000

Thanks a lot for the reference.
Too bad it's not documented anywhere in Philips' papers.

So it seems that the BEST result I can get with loading consecutive data 
from flash and storing at a port is 10 cycles...
(what with my 14.318MHz clock is ~230nS, actually a bit more then 3.7MHz).

Is there ANY way aroung it? Since I need a byte every oscillator cycle (3 
cpu cycles), the only way I see is to output 4 bytes at a time to pld and 
multiplex it 4 times - every oscillator cycle.

Any ideas?

BTW, is there any group archive anyhere?

Gennady


----- Original Message ----- 
From: "Robert Adsett" <subscriptions@...>
To: <lpc2000@yahoogroups.com>
Sent: Sunday, April 10, 2005 1:09 PM
Subject: Re: [lpc2000] port timing


>
> At 12:36 PM 4/10/05 -0400, Gennady Palitsky wrote:
>
>>Maybe someone can help me to clarify the question with GPIO timing.
>>
>>My intention is to move some data from flash to port0 on LPC2138 as fast 
>>as
>>possible.
>
> There have been multiple threads on this starting with "Simple test 
> program
> - is now instruction pipeline/VPB question" back in Nov of 2003.  An
> explanation from Philips appeared in the thread "I/O Speed - An
> Explanation" about a year later. Look up the actual message for the full
> explanation but quoting from it
>
> "The I/O speed has a maximum at ~3.7 Mhz because of several reasons, 
> .......
>
> It is caused by interactions between the
> ARM pipeline, the VPB bus, the ARM AHB wrapper (interface between the
> ARM7TDMI-S core and the AHB bus), and the instruction timing itself. "
>
> Robert
>
> " 'Freedom' has no meaning of itself.  There are always restrictions,   be
> they legal, genetic, or physical.  If you don't believe me, try to chew a
> radio signal. "  -- Kelvin Throop, III
> http://www.aeolusdevelopment.com/
>
>
>
>
> Yahoo! Groups Links
>
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>