Lpc2000

The THRE is set when the FIFO is empty. There may still be a BYTE in the 
transmit
shift register, but to keep the flow going you have to respond in less 
than 1 byte transmit
time to the THRE interrupt. If you don't there is nothing lost, the 
transmission just takes
a bit longer.

Regards,
Richard.


Bill Knight wrote:

> Am I missing something here guys (and gals)?  When the FIFO is
> enabled the THRE bit in the Line Status Register is set whenever
> the FIFO can accept additional characters.  So if it were clear,
> isn't that an indication the FIFO is full?
> As for RS-485 transceiver turn-around; the TEMT bit also in the
> Line Status Register, can be used to determine when the stop bit
> of the last character has been transmitted.  Can't that be used
> to control the RS-485 interface?
>
> Regards
> -Bill Knight
> R O SoftWare &
> http://www.theARMPatch.com
>
>
>
>
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