Lpc2000

At 09:41 AM 4/14/05 -0500, Bill Knight wrote:
>Am I missing something here guys (and gals)?  When the FIFO is
>enabled the THRE bit in the Line Status Register is set whenever
>the FIFO can accept additional characters.  So if it were clear,
>isn't that an indication the FIFO is full?

No, the THRE bit is cleared when something is ready to transmit, it is only 
set when the FIFO is empty.  The only way to fill the FIFO is to count how 
many bytes you put in.  I don't find that a big problem but it would be 
more efficient to be able to tell when the FIFO was full.

I'll leave the End of transmission question to others who have had to deal 
with it.  That still leaves the 9 bit mode problems.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,   be 
they legal, genetic, or physical.  If you don't believe me, try to chew a 
radio signal. "  -- Kelvin Throop, III
http://www.aeolusdevelopment.com/